Respected members, I have some doubts on Nios II processors. I am requesting the forum members to clarify my doubt. When designing NiosII processor system using SOPC builder, there is a on-chip ROM component inside the system. But the problem is that, the design is volatile, ie, when disconnecting the power, and again switching it on, again we need to program the FPGA. So my question is, what&#39;s the use of on-chip ROM. because whenever we there is a power off, data will vanish!!!. please suggest a solution for this.

Hello nipu_n, You are absolutely right that the on-chip ROM will lost the data after power-down the device. The data will be written into the ROM during config of the FPGA after power-on. So the configuration data holds the ROM data too. Bye, niosIIuser

> what&#39;s the use of on-chip ROM. There&#39;s no write enable ... so it won&#39;t get corrupted by code that doesn&#39;t play nice. Basically, it&#39;s useful for code/data that must remain consistent when a device (re)configuration does not occur (e.g. software reset/watchdog reset) ... otherwise, there&#39;s little motivation to use on-chip ROM over on-chip RAM. > because whenever we there is a power off, data will vanish! Well ... this is really depends on your point-of-view I guess ... but once the Cyclone/Stratix device is configured the on-chip ROM is available ... if the device isn&#39;t configured ... then it really doesn&#39;t matter ;-) Regards, --Scott

One other reason to select a ROM is in case you plan to move your design to Hardcopy. Hardcopy doesn&#39;t support initialized RAMs but does support ROMs.

hi nipu_n, in case your question is more basic: Altera FPGAs are SRAM-based devices, other vendors provide FLASH-based FPGAs. So SRAM-FPGAs looses its content everytime power is removed. Everytime power is connected, the FPGA needs to be configured, that means loaded with your specific design. Because on-chip ROM is part of your design, it is initialized while configuring the device. In a stand-alone application you have to add an extra FLASH-device (e.g. serial FLASH EPCSxx) which is programmed with your design and automatically loads your FPGA after power up (in milliseconds). Mike

thank you niosIIuser, smcnutt,James, and MiR for your valuable informations

nios II implementation problem | Altera Community

13 Replies

Altera_Forum
Honored Contributor
21 years ago
Thank you Slacker, Larsen, Mike and Wombat for your valuable suggestons.

I have a C-code for the 8051 microcontroller simulation. Whether can i implement it in NIOS II? If possible, how?

Please give some valuable informations....
Altera_Forum
Honored Contributor
21 years ago
I forget what 8051 code looks like, however the porting of the C code will mainly require changes to how you access peripherals, and whether or not your code was very dependent on what was previously available. So my answer is yes, but depending on the code it could be a simple or complex job. If the 8051 was memory mapped I/O (can't remember myself) then the port will not be too bad, and if this is not the case then some re-structuring may be needed (again it really depends on the code to be ported).

What does the 8051 in the system do? Also you may find that you just want to port the functionality and redo the code (might be more efficient the 2nd time around).
Altera_Forum
Honored Contributor
21 years ago
thank you BadOmen for ur suggestion.

i haven't gone thru the code for 8051. after going thru, i'll send details

thank you

Forum Discussion

nios II implementation problem

13 Replies

Recent Discussions

Nios V/g load-writeback hazard

Run-time errors using EMIF in Agilex 5 NIOS-V design

Ashling RISC Free IDE fails to download ELF file

Dual Port Nios V BSP error

set_output_delay explained for dummies