Altera_Forum
Honored Contributor
14 years agoNios II Data cache bypass
Hello,
I've created a SOPC component, where Avalon-MM slave port is connected directly to the Dual-Port RAM (1 read port, 1 write port). The hardware writes to the DPRAM and I want to reach that data from Nios. So far, so good, when I need to read data, i issue iord() and everything works fine, but I would like to use a pointer, so it would be easier to read the data:unsigned int * dma_data = (void *)(PCR_MONITOR_1_MEM_BASE | 0x80000000);As You can see, I am reading my component BASE address, plus added 31bit cache-bypass bit, but seems like I am wrong somewhere. When I start the CPU, the data read is OK, but when I change the memory contents, the data read out is wrong. I am reading somewhere in cache or there could be other problems? Thanks. P.S. I've enabled cache and burst accesses.