Forum Discussion
Altera_Forum
Honored Contributor
14 years agoI am new in FPGA design so don't know how to "correctly constrain" the design.
Could you give me some advises what should I do for the timing constrain? I have a camera (D5M) streaming data at 50MHz and NiosII Processor working at 100MHz to store the pixels in SDRAM (by DMA) and do some processing. What should I notice to this design? Thank you very much!