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Honored ContributorNios II Building Error
I got this error when building a Nios II project. Please help me fix it. :)
alt_sys_init.c:(.text+0x8): warning: Error: Interrupt not connected for JTAG_UART. You have selected the interrupt driven version of the ALTERA Avalon JTAG UART driver, but the interrupt is not connected for this device. You can select a polled mode driver by checking the 'small driver' option in the HAL configuration window, or by using the -DALTERA_AVALON_JTAG_UART_SMALL preprocessor flag.
alt_sys_init.c:(.text+0x8): undefined reference to `__alt_invalid'
collect2: ld returned 1 exit status
make: *** Error 1
21 Replies
Altera_ForumFrom a quick look it seems that your problem comes from the fact that you defined some of the I/O in the "clk" domain when those signals are generated from a different clock in the system, that has a different frequency. You should define all your I/O delays for the flash and SRAM I/O relative to the ssram_clk clock.
- Altera_Forum
I fixed all the failing paths, but Nios II failed to verify sram. :D
- Altera_Forum
Now you should run a memory test.
Are you sure your I/O timing constraints for the SRAM pins match the memory datasheet? - Altera_Forum
The memory test software also failed to verify sram. This is the first time I constraint the sram, but I think I do it correctly. I can send the project if you want to have a look. :D
- Altera_Forum
Without the hardware it will be difficult to debug the project... Which test is failing exactly? Do you have any error message?
- Altera_Forum
Hello World Small and Memory Test Small both gave this error:
Address 0x1200020 to 0x1201DAF was sram location. :DUsing cable "USB-Blaster ", device 1, instance 0x00 Pausing target processor: OK Initializing CPU cache (if present) OK Downloaded 8KB in 0.1s Verifying 01200020 ( 0%) Verify failed between address 0x1200020 and 0x1201DAF Leaving target processor paused - Altera_Forum
To do a memory test of SRAM you really want to load the test program to internal memory.
- Altera_Forum
Can you tell me specificly how to load program to internal memory? :)
- Altera_Forum
First you need an onchip memory in your system, connected to both the Nios CPU's instruction and data masters. Then in the BSP settings, set all the memory configurations to your on-chip memory. If the memory is small, select the small C option, and enable the compiler optimisations.
- Altera_Forum
Thank you for your guide. I successfully loaded the software to FPGA, and I got flash memory test failed:
And the sram memory test made the software crashed at this point:-Data bus test failed at bit 0x1
I don't know how to fix. :p-Data bus test passed -Address bus test passed -Byte and half-word access test passed -Testing each bit in memory device.
