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Altera_Forum
Honored Contributor
14 years agoNios II Building Error
I got this error when building a Nios II project. Please help me fix it. :)
alt_sys_init.c:(.text+0x8): warning: Error: Interrupt not connected for JTAG_UART. You have selected the interrup...
Altera_Forum
Honored Contributor
14 years agoFrom a quick look it seems that your problem comes from the fact that you defined some of the I/O in the "clk" domain when those signals are generated from a different clock in the system, that has a different frequency. You should define all your I/O delays for the flash and SRAM I/O relative to the ssram_clk clock.