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ZhiqiangLiang's avatar
ZhiqiangLiang
Icon for Occasional Contributor rankOccasional Contributor
6 months ago
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NIOS handle IRQ from FPGA register

Hi, I firstly created a new IP, and I add the interrupt sender FPGA_INTS. please see my picture below. I then connect the FPGA_INTS to irq of NIOS. Please see my picture below. The generated syste...
Nios Cpu
ZhiqiangLiang's avatar
ZhiqiangLiang
Icon for Occasional Contributor rankOccasional Contributor
6 months ago

@StefanG_Altera

I can understand your second paragraph about OR-combine the 32 interrupt. I will try this soon. Thank you!

I can't understand the first paragraph you posted.

Do you mean the ID -1 generated is correct?

Do you mean the C code in my upper post is correct?

In my IP source Verilog code, I do this:

bit [3:0] FPGA_INTS;
assign BFINTS = |FPGA_INTS;
However, in the generated system.h file, the ID is still -1. Please see the following picture.
how can I write ISR c code to handle this interrupt?
  • StefanG_Altera's avatar
    StefanG_Altera
    Icon for Occasional Contributor rankOccasional Contributor
    6 months ago

    In your case the IRQ line number BF5V_0_IRQ is not assigned ("-1"), despite being assigned a "4" in platfrom designer.

    Your component is exposing 32 bits (as you show in the component editor window), try OR-ing them inside your IP RTL and expose only one.

    The generated system.h file should reflect the IRQ line number and a non "-1" controller-ID, e.g.:

    #define BF5V_IRQ 4

    #define BF5V_IRQ_INTERRUPT_CONTROLLER_ID 0

    Your interrupt registration example code syntax looks correct to me.