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ZhiqiangLiang's avatar
ZhiqiangLiang
Icon for Occasional Contributor rankOccasional Contributor
6 months ago
Solved

NIOS handle IRQ from FPGA register

Hi,

I firstly created a new IP, and I add the interrupt sender FPGA_INTS. please see my picture below.

I then connect the FPGA_INTS to irq of NIOS. Please see my picture below.

The generated system.h file is shown in the following picture.

The questions:

1) I notice that a few xxxx_IRQ_INTERRUPT_CONTROLLER_ID are -1, and a few YYY_IRQ_INTERRUPT_CONTROLLER_ID are 0. No other value of XXX_IRQ_INTERRUPT_CONTROLLER_ID. is this correct?

2) the FPGA_INTS is assigned in my verilog code in the IP, and it is 32bit width which is 32 interrupt. how to write C code to accept each interrupt?

3) the FPGA_INTS is a 32bit-register in Verilog. The lowest 4bits of FPGA_INTS is useful, however Platform Designer reports error when I connect the 4bits FPGA_INTS interrupt to irq of NIOS II. so I extend the FPGA_INTS to 32bits in Verilog code and mask [28:4] bit of FPGA_INTS. is what I did correct?
unsigned int HD_irq_context;
void HD_interrupt_handler(void * HD_irq_context)
{
log("in HD interrupt == 0x%x\n", *((unsigned int*)HD_irq_context));
printf("==============================\n");
return;
}
void HD_interrupt_setup( void )
{
void * pISR_contex = ( void *) &HD_irq_context;
alt_ic_isr_register(
BF5V_0_IRQ_INTERRUPT_CONTROLLER_ID,
BF5V_0_IRQ,
HD_interrupt_handler,
pISR_contex,
0x0);
}

Nios Cpu

7 Replies

  • StefanG_Altera's avatar
    StefanG_Altera
    Icon for Occasional Contributor rankOccasional Contributor
    6 months ago

    Hi,

    1) Why do all xx_IRQ_INTERRUPT_CONTROLLER_ID values equal 0?

    In a standard Nios II system, there is only one interrupt controller: the internal interrupt controller. So all peripherals using interrupts will use the same controller ID. "-1" reflects peripherals not using interrupts at all.

    2 and 3) Nios II supports up to 32 independent HW interrupts with the std. IIC (internal interrupt controller).

    You can expose one "common" IRQ output from your IP component and internally OR-combine the 32 individual interrupt sources. Your ISR must poll internal status to identify the active interrupt (your IP should expose a status register to identify the source).

    As an alternative your IP could also expose 32 separate IRQ outputs (wiring in platform designer more tedious).

    In this case you register a separate ISR for each interrupt source. Each ISR only needs to handle one specific source, no need for polling a status register.

  • ZhiqiangLiang's avatar
    ZhiqiangLiang
    Icon for Occasional Contributor rankOccasional Contributor
    6 months ago

    @StefanG_Altera

    I can understand your second paragraph about OR-combine the 32 interrupt. I will try this soon. Thank you!

    I can't understand the first paragraph you posted.

    Do you mean the ID -1 generated is correct?

    Do you mean the C code in my upper post is correct?

    In my IP source Verilog code, I do this:

    bit [3:0] FPGA_INTS;
    assign BFINTS = |FPGA_INTS;
    However, in the generated system.h file, the ID is still -1. Please see the following picture.
    how can I write ISR c code to handle this interrupt?
    • StefanG_Altera's avatar
      StefanG_Altera
      Icon for Occasional Contributor rankOccasional Contributor
      6 months ago

      In your case the IRQ line number BF5V_0_IRQ is not assigned ("-1"), despite being assigned a "4" in platfrom designer.

      Your component is exposing 32 bits (as you show in the component editor window), try OR-ing them inside your IP RTL and expose only one.

      The generated system.h file should reflect the IRQ line number and a non "-1" controller-ID, e.g.:

      #define BF5V_IRQ 4

      #define BF5V_IRQ_INTERRUPT_CONTROLLER_ID 0

      Your interrupt registration example code syntax looks correct to me.

  • ZhiqiangLiang's avatar
    ZhiqiangLiang
    Icon for Occasional Contributor rankOccasional Contributor
    6 months ago

    @StefanG_Altera

    Thank you!

    I re-generate the IP, and re-generate the BSP.

    The problem is : the generated definition is as follows:

    why are they -1 but not 4 and 0?

  • tehjingy_Altera's avatar
    tehjingy_Altera
    Icon for Regular Contributor rankRegular Contributor
    6 months ago

    Hi


    I’m glad that your question has been addressed, I now transition this thread to community support. If you have a new question, Please login to ‘https://supporttickets.intel.com/s/?language=en_US’, view details of the desire request, and post a feed/response within the next 15 days to allow me to continue to support you. After 15 days, this thread will be transitioned to community support. The community users will be able to help you on your follow-up questions.


    Regards

    Jingyang, Teh