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Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
19 years ago

Nios custom component I/0 problem in DE2

Hi all,

I have added a simple component using SOPC Builder. The signals of the component are as follows 

 Port ( 
         clk   : in std_logic;
         reset : in std_logic;
  cs    : in std_logic;    
  wr    : in std_logic;
         din   : in std_logic_vector(31 downto 0);
  rd    : in std_logic;           
  dout  : out std_logic_vector(31 downto 0) );

I assigned clk and reset to global signals clk and reset.

cs, wr, din are assigned to chipselect, write and writedata of avalon_slave_0 interface and

rd, dout to read and readdata signals of avalon_slave_1 interface.

I perform input when cs and wr are high. But i find that cs and wr are never going high. I use following code to perform input and output. 

      en <= cs and wr;
     --Process for Input and output  
     process ( en, clk, reset)
     begin
    if (reset = &#39;1&#39;) then
     data_in <= (others => &#39;0&#39;);
    elsif (clk&#39;event and clk=&#39;0&#39;) then
  if ( en = &#39;1&#39;) then
      data_in <= din;
  end if;
                dount <= data_in;
      end

I access the custom logic using a C program. I run uClinux on the top of Nios processor. My C application runs on uClinux. My C program is very simple and just writes and reads the data. Program is shown below 

 main()
{
   int *p,*u;
   int i,k=0;
   p = 0x0090002C;
   u = 0x00900098;
   for ( i = 0; i < 10000; i++ )
   {
     
      *p = i;
       printf(" \n  Data_out: %x ", *u); 
   }
}

the same setup was working on stratix1s10 board. But it is not working on DE2 board. I tried read and write wait cycles of 0 and 1 for avalon interface. I tried sampling on negitive edge and also tried on positive edge. Nothing is working.

Can anyone help me.

2 Replies

  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    19 years ago

    Hi,

    I am sorry. I forgot to set the uncache bit. Now everything is working fine.

    sorry for the post.

    Regards,

    Mythri.

    --- Quote Start ---

    originally posted by mythri@Nov 4 2006, 06:18 PM

    hi all,

    i have added a simple component using sopc builder. the signals of the component are as follows 

     port ( 
         clk   : in std_logic;
         reset : in std_logic;
  cs    : in std_logic;    
  wr    : in std_logic;
         din   : in std_logic_vector(31 downto 0);
  rd    : in std_logic;           
  dout  : out std_logic_vector(31 downto 0) );

    i assigned clk and reset to global signals clk and reset.

    cs, wr, din are assigned to chipselect, write and writedata of avalon_slave_0 interface and

    rd, dout to read and readdata signals of avalon_slave_1 interface.

    i perform input when cs and wr are high. but i find that cs and wr are never going high. i use following code to perform input and output. 

          en <= cs and wr;
     --process for input and output  
     process ( en, clk, reset)
     begin
    if (reset = &#39;1&#39;) then
     data_in <= (others => &#39;0&#39;);
    elsif (clk&#39;event and clk=&#39;0&#39;) then
  if ( en = &#39;1&#39;) then
      data_in <= din;
  end if;
                dount <= data_in;
      end

    i access the custom logic using a c program. i run uclinux on the top of nios processor. my c application runs on uclinux. my c program is very simple and just writes and reads the data. program is shown below 

     main()
{
   int *p,*u;
   int i,k=0;
   p = 0x0090002c;
   u = 0x00900098;
   for ( i = 0; i < 10000; i++ )
   {
     
      *p = i;
       printf(" \n  data_out: %x ", *u); 
   }
}

    the same setup was working on stratix1s10 board. but it is not working on de2 board. i tried read and write wait cycles of 0 and 1 for avalon interface. i tried sampling on negitive edge and also tried on positive edge. nothing is working.

    can anyone help me.

    <div align='right'><{post_snapback}> (index.php?act=findpost&pid=19160)</div>

    --- Quote End ---

  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    19 years ago

    --- Quote Start ---

    originally posted by mythri@Nov 4 2006, 08:48 AM

    hi all,

    i have added a simple component using sopc builder. the signals of the component are as follows 

     port ( 
         clk   : in std_logic;
         reset : in std_logic;
  cs    : in std_logic;    
  wr    : in std_logic;
         din   : in std_logic_vector(31 downto 0);
  rd    : in std_logic;           
  dout  : out std_logic_vector(31 downto 0) );

    i assigned clk and reset to global signals clk and reset.

    cs, wr, din are assigned to chipselect, write and writedata of avalon_slave_0 interface and

    rd, dout to read and readdata signals of avalon_slave_1 interface.

    i perform input when cs and wr are high. but i find that cs and wr are never going high. i use following code to perform input and output. 

          en <= cs and wr;
     --process for input and output  
     process ( en, clk, reset)
     begin
    if (reset = &#39;1&#39;) then
     data_in <= (others => &#39;0&#39;);
    elsif (clk&#39;event and clk=&#39;0&#39;) then
  if ( en = &#39;1&#39;) then
      data_in <= din;
  end if;
                dount <= data_in;
      end

    i access the custom logic using a c program. i run uclinux on the top of nios processor. my c application runs on uclinux. my c program is very simple and just writes and reads the data. program is shown below 

     main()
{
   int *p,*u;
   int i,k=0;
   p = 0x0090002c;
   u = 0x00900098;
   for ( i = 0; i < 10000; i++ )
   {
     
      *p = i;
       printf(" \n  data_out: %x ", *u); 
   }
}

    the same setup was working on stratix1s10 board. but it is not working on de2 board. i tried read and write wait cycles of 0 and 1 for avalon interface. i tried sampling on negitive edge and also tried on positive edge. nothing is working.

    can anyone help me.

    <div align='right'><{post_snapback}> (index.php?act=findpost&pid=19160)</div>

    --- Quote End ---

    Hi,mythri

    I&#39;m Nios Newbie. I want added a simple component using SOPC Builder.

    Can you give me a complete simple example?

    thanks.

    Regards

    faye