Honored Contributor
Honored Contributor
i have added a simple component using sopc builder. the signals of the component are as follows
port (
clk : in std_logic;
reset : in std_logic;
cs : in std_logic;
wr : in std_logic;
din : in std_logic_vector(31 downto 0);
rd : in std_logic;
dout : out std_logic_vector(31 downto 0) );
i assigned clk and reset to global signals clk and reset.
cs, wr, din are assigned to chipselect, write and writedata of avalon_slave_0 interface and
rd, dout to read and readdata signals of avalon_slave_1 interface.
i perform input when cs and wr are high. but i find that cs and wr are never going high. i use following code to perform input and output.
en <= cs and wr;
--process for input and output
process ( en, clk, reset)
begin
if (reset = '1') then
data_in <= (others => '0');
elsif (clk'event and clk='0') then
if ( en = '1') then
data_in <= din;
end if;
dount <= data_in;
end
i access the custom logic using a c program. i run uclinux on the top of nios processor. my c application runs on uclinux. my c program is very simple and just writes and reads the data. program is shown below
main()
{
int *p,*u;
int i,k=0;
p = 0x0090002c;
u = 0x00900098;
for ( i = 0; i < 10000; i++ )
{
*p = i;
printf(" \n data_out: %x ", *u);
}
}
the same setup was working on stratix1s10 board. but it is not working on de2 board. i tried read and write wait cycles of 0 and 1 for avalon interface. i tried sampling on negitive edge and also tried on positive edge. nothing is working.
can anyone help me.
<div align='right'><{post_snapback}> (index.php?act=findpost&pid=19160)</div> --- Quote End --- Hi,mythri I'm Nios Newbie. I want added a simple component using SOPC Builder. Can you give me a complete simple example? thanks. Regards faye
