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Altera_Forum
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Honored ContributorNIOS assisting FPGA design
Hi everyone, I have a question as a beginner.
Could I design FPGA circuits using NIOS2 stratix developement kit http://forum.niosforum.com/work2/style_emoticons/<#EMO_DIR#>/huh.gif I already had a verilog code for a filter and I downloaded it directly to the board by JTAG cable. But I did not know how to observe the performance of my circuits. Help wanted4 Replies
Altera_ForumI ran the altera Nios2 training exercise: SignalTap II Lab on the NIOS2 developement board.
The objective of this exercise was to help us with understanding a debug tool. My question is that I could not run the code: counter.vhdl correctly. The messeage was that they were waiting the clock. I did everything based on the training guide. Just loading the counter.vhdl code to the board while building the signalTap II file. No testbench code. How do I do now?- Altera_Forum
What does counter;vhd actually does? Do you have some testpins connected to an oscilloscope?
Just a question : do you have enough experience to make a blinking led on the demo board? If not, I should start with trying that before going to NIOS. Stefaan. - Altera_Forum
of course, there is some interconnconetion between nios chip and oscillator, but I did not write some codes to be a controller. Then I think there is no connection between them.
- Altera_Forum
Do you have a clock net in your project? Is it connected to the correct pin of the chip,
Stefaan,
