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Altera_Forum
Honored Contributor
Honored ContributorNIOS assisting FPGA design
Hi everyone, I have a question as a beginner. Could I design FPGA circuits using NIOS2 stratix developement kit http://forum.niosforum.com/work2/style_emoticons/<#EMO_DIR#>/huh.gif ...
Altera_ForumHonored Contributor
Honored ContributorI ran the altera Nios2 training exercise: SignalTap II Lab on the NIOS2 developement board.
The objective of this exercise was to help us with understanding a debug tool. My question is that I could not run the code: counter.vhdl correctly. The messeage was that they were waiting the clock. I did everything based on the training guide. Just loading the counter.vhdl code to the board while building the signalTap II file. No testbench code. How do I do now?
