NIOS assisting FPGA design

I ran the altera Nios2 training exercise: SignalTap II Lab on the NIOS2 developement board.

The objective of this exercise was to help us with understanding a debug tool.

My question is that I could not run the code: counter.vhdl correctly. The messeage was that they were waiting the clock. I did everything based on the training guide. Just loading the counter.vhdl code to the board while building the signalTap II file. No testbench code. How do I do now?