NIOS 2 GERMS

Add "Legacy On Chip Memory" under "Legacy Components" and set contents to GERMS. Works great!

Works over JTAG or serial.

Ken

Either use what KenLand said or use the Jtag uart. Using the Jtag uart is very simple since it can be used with printf and scanf (open helloworld.c to see an example of outputting from the NIOS II to the console).

Either way though, if you try the Jtag uart and it doesn't work right away for you then just go with GERMS (if you want GERMS so that you can just download your code easily then it's even easier with the Jtag UART)

***Edit: Cool my emoticon finally shows up http://forum.niosforum.com/work2/style_emoticons/<#EMO_DIR#>/smile.gif ***

Although, I read something in a manual from Altera that the Legacy development flow is not supported by NiosII/f.

Is this just to have not too much questions from people who don&#39;t understand data cache and its consequences for accessing peripherals, or is there an other reason?

I seem to have problems whith interrupt behaviour that is not stable in the f version, but it is in the s version.

I&#39;ve used the /f in legacy mode to try and get more performance. If you can&#39;t or don&#39;t want to get the data cache coherency perfect you can turn off data cache with the .ptf setting "always_bypass_dcache"

Here&#39;s a link to the thread where James told me about it:

turn off data cache in nii/f (http://www.niosforum.com/forum/index.php?act=st&f=2&t=535)

FYI, I didn&#39;t get any additional performance from the /f over the /s with dcache turned OFF. For the part of my code I had running with dcache ON there was a 3X speedup. (Really only a small wait-for-event loop rechecking the same flags over and over)

But you know what svhb? The dcache ON problems I had could be atributable to IRQ problems, because everything seemed to work, but the througput of my IRQ based USB chip went to almost nothing. You might try the .ptf setting and see if your IRQ problem goes away.

Ken

Thanks for the comment.

But I think I don&#39;t do anything wrong with the DCache in the interrupt routine (if the cache works as expected of course).

I even tried with STWIO and LDWIO instructions instead of the LDW and STW for the part that goes wrong.

It looks more like an internal timing problem (randomness, ...) but after fitting, the timing looks ok.

I&#39;ll try with the DCache disabled.

Stefaan