Forum Discussion
Altera_Forum
Honored Contributor
21 years agoThanks for the comment.
But I think I don't do anything wrong with the DCache in the interrupt routine (if the cache works as expected of course). I even tried with STWIO and LDWIO instructions instead of the LDW and STW for the part that goes wrong. It looks more like an internal timing problem (randomness, ...) but after fitting, the timing looks ok. I'll try with the DCache disabled. Stefaan