NIOS + IRQ + custom component

I would start by reading through this section of the handbook and practicing using an input PIO as an interrupt source:

http://www.altera.com/literature/hb/nios2/n2sw_nii52006.pdf

If you need additional help shoot me a pm with your email address and I'll send you a test design that contains a random IRQ generator I created a while back for reasons I can't really remember :)

Tks, BadOmen, I am reading.

I can't PM, but you can email the example to

frodobolsonxx (at) gmail (dot) com

Tks again jairo

Hi,

I would appreciate a copy of the example SOPC custom component with IRQ , if available.

please send to: kered95 at gmail dot com

Thanks.

Thanks BadOmen,

Much appreciated.

Ken.

:)

Hi,

Please send the example SOPC custom component with IRQ to rgjokerit at gmail dot com.

Thanks.

Hi,

Please send the example SOPC custom component with IRQ to alexandrvb58 at gmail dot com.

Thanks.

Seems to me that you should be doing your own assignments.

Remember your tutor will also be reading the forum!

Hi, now I'm also trying to interrupt the CPU with my custom component.

So my custom component consists of this following blocks :

1. FIFO, this FIFO receives input from outside SOPC and send the output to DMA

2. Write_control, to control how the FIFO writes its data

After a certain number of data (for example 10) have been written in the FIFO, the FIFO should send an interrupt signal to CPU. I've provided an irq signal (the interface type is 'interrupt sender', the interrupt signal's width is one clock) and connected it to the CPU's interrupt receiver interface.

My question is in the interrupt sender properties, which Avalon MM slave that I have to assign? Is it the Avalon MM slave of the FIFO output data interface?

I've tried to assign the Avalon MM slave of the FIFO output data in the interrupt sender properties. I also have written the interrupt handler C code like shown in Quartus manual.

However my design didn't work. Does anyone have any suggestion for me?

Thank you