NIOS + IRQ + custom component

Hi, now I'm also trying to interrupt the CPU with my custom component.

So my custom component consists of this following blocks :

1. FIFO, this FIFO receives input from outside SOPC and send the output to DMA

2. Write_control, to control how the FIFO writes its data

After a certain number of data (for example 10) have been written in the FIFO, the FIFO should send an interrupt signal to CPU. I've provided an irq signal (the interface type is 'interrupt sender', the interrupt signal's width is one clock) and connected it to the CPU's interrupt receiver interface.

My question is in the interrupt sender properties, which Avalon MM slave that I have to assign? Is it the Avalon MM slave of the FIFO output data interface?

I've tried to assign the Avalon MM slave of the FIFO output data in the interrupt sender properties. I also have written the interrupt handler C code like shown in Quartus manual.

However my design didn't work. Does anyone have any suggestion for me?

Thank you