*NEWBIE* User Logic

Hello,

timescale 1ns / 100ps
module mytestmodule (
               // inputs:
    address,
                write_data,
               // outputs:
                read_data
             );
  output   read_data;
  input    write_data;
  input    address;
  wire     read_data;
  assign read_data = write_data + 1;
endmodule

#include <stdio.h># include <C:\altera\kits\nios2\bin\eclipse\workspace\uCLinux_Kernel\build\include\nios2_system.h>
# define ul_base 0x009208E0
typedef volatile struct
 {
  unsigned char adress; // 2 bit address
  unsigned long int write_data; // 32 bit writeable data
  unsigned long int read_data; // 32 bit readable data
 } userlogic;
 
int main (void) {
 userlogic *ul = ul_base;
 
 
 unsigned long int i;
 for (i = 0; i <= 4; i++) {
   ul->write_data = i;
   printf("write_data=%ld --> read_data=%ld\n", i, ul->read_data);
 }
 return 0;
 
}