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Altera_Forum's avatar
Altera_Forum
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21 years ago

*NEWBIE* User Logic

Hello, I created a very simple user logic. I takes the input, adds 1 to it and write it to the output. timescale 1ns / 100ps module mytestmodule ( // inputs: address,...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
21 years ago

I'll assume the hardware works (I'm one of the few North Americans that use VHDL lol).

But looking at your software, if you are using data cache, then you are not bypassing it. For register access declare your pointers volatile (so they don't get synthesized away), and use the IORD and IOWR commands to bypass the data cache. Here is the syntax:

IORD(base, offset);

IOWR(base,offset,data);

Base is the base address of your hardware, offset is the address within the address space of your hardware (offset from the base), and data is the data you will be writing. These are the 32 bit calls, they have others for 8 and 16 bit operations as well.

Cheers.