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Altera_Forum's avatar
Altera_Forum
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21 years ago

*NEWBIE* User Logic

Hello, I created a very simple user logic. I takes the input, adds 1 to it and write it to the output. timescale 1ns / 100ps module mytestmodule ( // inputs: address,...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
21 years ago

Write data isn't guaranteed to be stable when write is negated.

So you need to latch ... Try this: 

module mytestmodule (clk, address, write, writedata, readdata);
input clk;
input  address;
input write;
input    writedata;
output   readdata;
wire clk;
wire  address;
wire write;
wire  writedata;
wire  readdata;
reg  dreg;
always @(posedge clk)
    if (write) dreg <= writedata;
assign readdata = dreg + 1;
endmodule

--Scott