multi Nios connect to One Pcie

Using a shared memory between several SOPC/QSYS seems extremely complicated for me. You'd need to write custom components that implement Avalon masters and slaves and open a communication between the different systems, but you would have to do yourself all the memory mapping if you indend to share more than a memory, and possibly have to cope with different addresses on each CPU... I think it is far easier to put everything in a single QSys design, using subdesigns for each CPU as Socrates suggests.