Hi all! I'm creating a design that uses a Nios II processor with on board memory and wish to be able to read & write to the on-chip memory from custom Verilog. I did originally try using the Altera MM templates however as discussed by other users (search for 'Avalon MM templates in Qsys' on this forum), I experienced problems so have switched to using the mSGDMA template. My question is what ports should I be exporting to use in the my custom Verilog? Thanks, probably a simple question for someone!

I suspect it is just the descriptor_slave port that needs written to. Is this correct?

I'm guessing you would want to expose the master data streaming port so that you can move data back and forth and the descriptor slave port so that you can instruction the DMA where it should be reading/writing. I'm assuming you are moving a block of data at a time to/from the on-chip RAM. If you are just performing random word accesses to the on-chip RAM then there is no point involving a DMA, just use a master interface in that case. Since you are accessing on-chip memory are you sure you don't want to just create a master interface and have your logic access it directly? Since your custom logic already knows where it wants to transfer data it's not much more than just an address (up) counter, a length (down) counter, and control logic that pauses the counters when waitrequest is asserted to recreate DMA types of transfers. If you describe what you are trying to do we can probably give you pointers of what to do.

Hi BadOmen Thanks for your reply. Yes, random word access sounds like a good idea, so I'd like to create a master interface. I did try to use the templates here (altera.com/support/examples/nios2/exm-avalon-mm.html) however they did not seem to work. A pointer of where to start would be very helpful!

Those templates basically implement half a DMA but by the sounds of it that doesn't sound like what you want. That Avalon-MM specification is fairly flexible so you just include the signals that you need. If you want just a simple master interface you'll just need address, read, write, byteenable, readdata, writedata, and waitrequest. If you want higher performance add the readdatavalid signal which will allow your master to post multiple reads before data returns. So the first step is just to determine whether you need high performance reads. If the logic responsible for reads and writes can work independently you may want to implement two masters, one dedicated to reads and another for writes. Waitrequest is the most important signal to pay attention to, any time you are posting a read or write if waitrequest is asserted then you must continue to hold read/write high and keep the address, byte enables, and write data (if it's a write access) constant until waitrequest deasserts itself. When waitrequest is low and read/write is high then you consider that transfer complete and can move on to the next location you want to access. I recommend reading the Avalon-MM specification, it'll have more details. Essentially the logic you would have needed to control the master templates gets you half way to having a custom master, the other half is just making sure you heed waitrequest.

I have implemented a memory master using the template from Qsys new component wizard. I've attached a screenshot of my signals from ModelSim when I'm writing to the on-chip memory. However when I access the same location using C code from the Nios II the value doesn't seem to have written. Do these signals look correct to you? Many thanks!

mSGDMA and On-chip Memory | Altera Community

18 Replies

Altera_Forum
Honored Contributor
13 years ago
I suspect it is just the descriptor_slave port that needs written to. Is this correct?
Altera_Forum
Honored Contributor
13 years ago
I'm guessing you would want to expose the master data streaming port so that you can move data back and forth and the descriptor slave port so that you can instruction the DMA where it should be reading/writing. I'm assuming you are moving a block of data at a time to/from the on-chip RAM. If you are just performing random word accesses to the on-chip RAM then there is no point involving a DMA, just use a master interface in that case. Since you are accessing on-chip memory are you sure you don't want to just create a master interface and have your logic access it directly? Since your custom logic already knows where it wants to transfer data it's not much more than just an address (up) counter, a length (down) counter, and control logic that pauses the counters when waitrequest is asserted to recreate DMA types of transfers. If you describe what you are trying to do we can probably give you pointers of what to do.
Altera_Forum
Honored Contributor
13 years ago
Hi BadOmen

Thanks for your reply.

Yes, random word access sounds like a good idea, so I'd like to create a master interface. I did try to use the templates here (altera.com/support/examples/nios2/exm-avalon-mm.html) however they did not seem to work. A pointer of where to start would be very helpful!
Altera_Forum
Honored Contributor
13 years ago
Those templates basically implement half a DMA but by the sounds of it that doesn't sound like what you want.

That Avalon-MM specification is fairly flexible so you just include the signals that you need. If you want just a simple master interface you'll just need address, read, write, byteenable, readdata, writedata, and waitrequest. If you want higher performance add the readdatavalid signal which will allow your master to post multiple reads before data returns. So the first step is just to determine whether you need high performance reads.

If the logic responsible for reads and writes can work independently you may want to implement two masters, one dedicated to reads and another for writes. Waitrequest is the most important signal to pay attention to, any time you are posting a read or write if waitrequest is asserted then you must continue to hold read/write high and keep the address, byte enables, and write data (if it's a write access) constant until waitrequest deasserts itself. When waitrequest is low and read/write is high then you consider that transfer complete and can move on to the next location you want to access.

I recommend reading the Avalon-MM specification, it'll have more details. Essentially the logic you would have needed to control the master templates gets you half way to having a custom master, the other half is just making sure you heed waitrequest.
Altera_Forum
Honored Contributor
13 years ago
I have implemented a memory master using the template from Qsys new component wizard. I've attached a screenshot of my signals from ModelSim when I'm writing to the on-chip memory. However when I access the same location using C code from the Nios II the value doesn't seem to have written. Do these signals look correct to you?

Many thanks!
Altera_Forum
Honored Contributor
13 years ago
Looks fine to me, I suspect you used IORD and passed in an offset of 0x100000? IORD uses 32-bit word offsets so you might have just accessed the wrong location.

I avoid IORD/IOWR and use the direct macros instead IORD_32DIRECT/IOWR_32DIRECT. Those ones you byte offsets so if that was your issue you should be able to just replace the macro and it should work.
Altera_Forum
Honored Contributor
13 years ago
Also you should probably include byte enables, when you don't include them the tools assume that you are performing full word accesses. I would include them anyway and hardcode them high just in case you ever need to perform partial word accesses later down the road.
Altera_Forum
Honored Contributor
13 years ago
Adding the template from Qsys didn't give me the parameter of byte enables, how would I add this in?

I forgot my Nios II program would also be stored in the memory, which was overwriting my data, doh! It's working now. Many thanks for your help!
Altera_Forum
Honored Contributor
13 years ago
That's a common mistake, anyone that has worked with DMAs would be lying if they claimed they have never have done that :)

If you create a linker region you can have the CPU avoid putting code or data in that region if you want to share that memory with the external master. I forget how to do that in the linker script but the Nios II BSP editor should make that easier since it's graphical.

* edit * Missed that part about the template. I wasn't aware the templates didn't have byte enables (oops). For now it would be just a matter of adding one one more signal to the template 'byteenable' and mapping it to the 'byteenable' Avalon-MM type. Then in the HDL you would just assign all ones to it. The width of the signal would be "DATA_WIDTH/8" so to assign a varible set of all ones you could do this:

assign byteenable = {(DATA_WIDTH/8){1'b1}}; // takes '1' and replicates it (DATA_WIDTH/8) times
Altera_Forum
Honored Contributor
9 years ago
Hi BadOmen and all,

I am using cyclone V SOC kit from Terasic.

Currently I am searching for method to get high latency and thoughput, otherthan AXI bridges.

Currentlly, I am using AXI bridge to communicate between FPGA and HPS; but I found this bridge seems to work with low latency. I made hps to fpga bridge connection for Light weight hps to FPGA communication.

P.S : I go through exaple of Datamover; but I found it bit complicated.

Could you please suggest me best method to communicate between HPS and FPGA for higher latency and higher thoughput.

can I use datamover? ( https://rocketboards.org/foswiki/view/projects/datamover )

Thanks in advance.

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