mSGDMA and On-chip Memory

I'm guessing you would want to expose the master data streaming port so that you can move data back and forth and the descriptor slave port so that you can instruction the DMA where it should be reading/writing. I'm assuming you are moving a block of data at a time to/from the on-chip RAM. If you are just performing random word accesses to the on-chip RAM then there is no point involving a DMA, just use a master interface in that case. Since you are accessing on-chip memory are you sure you don't want to just create a master interface and have your logic access it directly? Since your custom logic already knows where it wants to transfer data it's not much more than just an address (up) counter, a length (down) counter, and control logic that pauses the counters when waitrequest is asserted to recreate DMA types of transfers. If you describe what you are trying to do we can probably give you pointers of what to do.