mSGDMA and On-chip Memory

Those templates basically implement half a DMA but by the sounds of it that doesn't sound like what you want.

That Avalon-MM specification is fairly flexible so you just include the signals that you need. If you want just a simple master interface you'll just need address, read, write, byteenable, readdata, writedata, and waitrequest. If you want higher performance add the readdatavalid signal which will allow your master to post multiple reads before data returns. So the first step is just to determine whether you need high performance reads.

If the logic responsible for reads and writes can work independently you may want to implement two masters, one dedicated to reads and another for writes. Waitrequest is the most important signal to pay attention to, any time you are posting a read or write if waitrequest is asserted then you must continue to hold read/write high and keep the address, byte enables, and write data (if it's a write access) constant until waitrequest deasserts itself. When waitrequest is low and read/write is high then you consider that transfer complete and can move on to the next location you want to access.

I recommend reading the Avalon-MM specification, it'll have more details. Essentially the logic you would have needed to control the master templates gets you half way to having a custom master, the other half is just making sure you heed waitrequest.