Mixing Verilog and VHDL

I have to connect logic written in Verilog with logic written in VHDL.

I've tried with Quartus 4.1.

here is the code of the Verilog file:

dsp_dummy    dsp_dummy_inst (
    .clock ( clock ),
    .reset ( null ),
    .enable ( eins ),
    .stall ( null ),
    .wb_dat_io ( wb_dat_io ),
    .wb_adr_i ( address_mem ),
    
    
    .wb_we_i ( wb_we_i ),
    .wb_stb_i ( wb_stb_i ),
    .wb_ack_o ( wb_ack_o )
    
    );

I've added the file dsp_dummy.vhdl to the project. When I try to compile it, I get the following error:

Error: Node instance dsp_dummy_inst instantiates undefined entity dsp_dummy

I don't know, what I've done wrong. Can anyone help me?