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Altera_Forum
Honored Contributor
Honored ContributorMixing Verilog and VHDL
I have to connect logic written in Verilog with logic written in VHDL. I've tried with Quartus 4.1. here is the code of the Verilog file: dsp_dummy dsp_dummy_inst (
.clock ( cl...
Altera_ForumHonored Contributor
Honored Contributorcheck the bdf or the pin list.
That's the error I get when I don't have something hooked up right.
