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aiedb's avatar
aiedb
Icon for Occasional Contributor rankOccasional Contributor
8 months ago

max10 RSU without nios

hii is there a documentation that show the work flow that i need in order to perform MAX10 rsu without the help of nios ii , with my discrete logic ???
Nios Cpu
KalenB_Altera's avatar
KalenB_Altera
Icon for New Contributor rankNew Contributor
8 months ago

Hi Aiebd,

Section 5.2 of the Dual Config IP mentions the registers and fields. Here's a link: https://www.intel.com/content/www/us/en/docs/programmable/683865/current/dual-configuration-core-memory-mapped.html

The relevant registers for your question are at word address 0 and 1. I've coped them below:

Offset R/W Width (Bits) Description

0W32
  • Bit 0—Trigger reconfiguration.
  • Bit 1—Reset the watchdog timer.
  • Bit 31:2—Reserved.
Signals are triggered at the same write cycle on Avalon® .
1W32
  • Bit 0—Trigger config_sel_overwrite value to the input register.
    • 0: Disable overwrite config_sel pin.
    • 1: Enable overwrite config_sel pin.
  • Bit 1—Writes config_sel value to the input register. Set 0 or 1 to load from configuration image 0 or 1 respectively
    • 0: Load configuration image 0.
    • 1: Load configuration image 1.
  • Bit 31:2—Reserved.
The busy signal is generated right after the write cycle, while the configuration image information is registered. Once the busy signal is high, writing to this address is ignored until the process is completed and the busy signal is de-asserted.
  • aiedb's avatar
    aiedb
    Icon for Occasional Contributor rankOccasional Contributor
    7 months ago

    hii thanks for your reply , i will try to built my own fsm and see how it will work for me