max10 RSU without nios

Question

hii is there a documentation that show the work flow that i need in order to perform MAX10 rsu without the help of nios ii , with my discrete logic ???

kalenb_altera · Answer

Hi Aiebd,RSU on Max 10 has two key steps; 1) Write the new image to flash via the User Flash Memory IP (https://www.intel.com/content/www/us/en/docs/programmable/683180/18-0/on-chip-flash-core-references.html) and 2) Identifying to the configuration system what CFM to use on the next nConfig and trigger reconfiguration via the Dual Configuration IP (https://www.intel.com/content/www/us/en/docs/programmable/683865/current/dual-configuration-core-26199.html).You could definitely use an FSM to do these operations. I hope these user guides help give you the info you need.

aiedb · Answer

hii thanks a lot for help

lets say i want to write my own fsm to trigger an rsu after writing my image to cfm0 and cfm 1/2 what are the registers that i need to work with in order to :

1- trigger the nconfig ?

2-to choose from which cfm that fpga get configured ?

kalenb_altera · Answer

Hi Aiebd,Section 5.2 of the Dual Config IP mentions the registers and fields. Here's a link: https://www.intel.com/content/www/us/en/docs/programmable/683865/current/dual-configuration-core-memory-mapped.htmlThe relevant registers for your question are at word address 0 and 1. I've coped them below:Offset R/W Width (Bits) Description0W32Bit 0—Trigger reconfiguration.Bit 1—Reset the watchdog timer.Bit 31:2—Reserved.Signals are triggered at the same write cycle on Avalon® .1W32Bit 0—Trigger config_sel_overwrite value to the input register.0: Disable overwrite config_sel pin.1: Enable overwrite config_sel pin.Bit 1—Writes config_sel value to the input register. Set 0 or 1 to load from configuration image 0 or 1 respectively0: Load configuration image 0.1: Load configuration image 1.Bit 31:2—Reserved.The busy signal is generated right after the write cycle, while the configuration image information is registered. Once the busy signal is high, writing to this address is ignored until the process is completed and the busy signal is de-asserted.

aiedb · Answer

hii thanks for your reply , i will try to built my own fsm and see how it will work for me

kennyt_altera · Answer

Do you have further question? If no, we shall close this thread.

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max10 RSU without nios

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0	W	32	Bit 0—Trigger reconfiguration. Bit 1—Reset the watchdog timer. Bit 31:2—Reserved. Signals are triggered at the same write cycle on Avalon® .
1	W	32	Bit 0—Trigger config_sel_overwrite value to the input register. 0: Disable overwrite config_sel pin. 1: Enable overwrite config_sel pin. Bit 1—Writes config_sel value to the input register. Set 0 or 1 to load from configuration image 0 or 1 respectively 0: Load configuration image 0. 1: Load configuration image 1. Bit 31:2—Reserved. The busy signal is generated right after the write cycle, while the configuration image information is registered. Once the busy signal is high, writing to this address is ignored until the process is completed and the busy signal is de-asserted.