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Altera_Forum's avatar
Altera_Forum
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19 years ago

Max clock frequency

Hi

We have a design which is more or less based on the Stratix II dev. kit from Altera (same memory and Ethernet chips etc)

The NIOS clock freq. is set to 50.0 MHz just as in the dev. kit.

What would be the upper NIOS II clock freq supported for this design?

-jan

1 Reply

  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    19 years ago

    Hard to say,

    This depends mostly on the number of peripherals connected to the Avalon bus. For every peripheral, an entrie is added to the input mux from the connected master. The larger the mux grow, the slower it gets.

    You can have a look at the compilation report in the timing analyzer entry. If it says for example 73.5MHz, try with 80Mc as clock source. The compiling process will do more effort then to try to meet the timing requirements.