Forum Discussion
Honored Contributorjtag_uart isn't simulated by ModelSim.
I want to simulate my application from Nios II SBT. I've done successful an example from AN351 and try to repeat it with my Development Kit (Nios II Embedded Evaluation Kit (NEEK), Cyclone III Edition) using Standard design example and "Hello world" application. But I got result - all components are simulated (Nios II, DDR e.t.c) but jtag_uart module keeps silence and "Hello world" isn't appeared.
I use Standard from a disc from of board and got this result. I downloaded updates "Nios II Embedded Evaluation Kit v8.0" and tried to simulate, but got the same result. But it's interesting: Simulation was successful when I used design examples from Nios II SBT from folder \nios2eds\examples (niosII_cycloneII_2c35 and niosII_stratixII_2s60). I did't a find solution here (or may be didn't see). May be somebody knows how solve this problem?18 Replies
Altera_ForumHi:
I have the same problem with neek and modelsim simulations. NO SOLUTIONS FOR US UNTIL NOW.- Altera_Forum
Does anybody know how to solve this problem? Or nobody has met it?
- Altera_Forum
can you write down the steps from beginning until the simulation start?
Are you run this from Nios2 SBT GUI or Nios2-IDE or from command line? - Altera_Forum
For simulation my system I use an351-Simulating Nios II Embedded Processor Design step=-by-step. I've tried to run from SBT GUI and Command line, but have no success( What about you? Was it successful?
- Altera_Forum
I'm having the same problem...silent jtag_uart...
win7+quartus10.0sp1+modelsim6.6c - Altera_Forum
...I just ran the simulation for longer...2000us and finally saw jtag output
- Altera_Forum
Thanks for your advice! I'll try it and will write results.
- Altera_Forum
Attempt was unsuccessful. I ran the simulation for 5000us, but didn't see jtag output (during all time jtag wasn't changing the state)
to benner4520 What project and design did you use? Before I simulated my component in previos design (Cyclone II 2c35 from nios II IDE examples folder) - Altera_Forum
I believe I had made a project from scratch and included only the Nios II, SDRAM controller (will external PLL), the jtag_uart, and maybe some PIOs and the RS232 controller. Make sure to check all boxes for simulation in the SOPC builer.
Does your Nios IDE map your streams to the jtag when using printf for char output or are you trying something different. Do you see other signals changing in the system? - Altera_Forum
Which components has options "simulation"? I saw only in pio-component.
I've tried to create a new system for Cyclone III with NiosII, SDRAM controller (DDR SDRAM High-Perfomance controller), clock-briges and my component (mac). I've attached a structure of my SOPC-project. Clocks are used the same, like an original standart NEEK design. But this attempt was unseccessful too ( Is it critical to use an internal clock for SDRAM-controller? Because DDR Sdram Controller MegaCore uses pll clock in CycloneII_NiosII design from standart Nios II examples Stdin,stdout uses jtag_uart. Therefore I suppose printf should use jtag_uart too.
