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Altera_Forum
Honored Contributor
Honored Contributorjtag_uart isn't simulated by ModelSim.
I want to simulate my application from Nios II SBT. I've done successful an example from AN351 and try to repeat it with my Development Kit (Nios II Embedded Evaluation Kit (NEEK), Cyclone III Editio...
Altera_ForumHonored Contributor
Honored ContributorWhich components has options "simulation"? I saw only in pio-component.
I've tried to create a new system for Cyclone III with NiosII, SDRAM controller (DDR SDRAM High-Perfomance controller), clock-briges and my component (mac). I've attached a structure of my SOPC-project. Clocks are used the same, like an original standart NEEK design. But this attempt was unseccessful too ( Is it critical to use an internal clock for SDRAM-controller? Because DDR Sdram Controller MegaCore uses pll clock in CycloneII_NiosII design from standart Nios II examples Stdin,stdout uses jtag_uart. Therefore I suppose printf should use jtag_uart too.
