jtag_uart isn't simulated by ModelSim.

Which components has options "simulation"? I saw only in pio-component.

I've tried to create a new system for Cyclone III with NiosII, SDRAM controller (DDR SDRAM High-Perfomance controller), clock-briges and my component (mac). I've attached a structure of my SOPC-project. Clocks are used the same, like an original standart NEEK design. But this attempt was unseccessful too (

Is it critical to use an internal clock for SDRAM-controller? Because DDR Sdram Controller MegaCore uses pll clock in CycloneII_NiosII design from standart Nios II examples

Stdin,stdout uses jtag_uart. Therefore I suppose printf should use jtag_uart too.