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Altera_Forum's avatar
Altera_Forum
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17 years ago

"IORD_8DIRECT" reads 32 Bit ?

Hi,

(I've tried to find something related to my problem, but without success. So I'm sorry if there is already a thread about this!)

I've connected a parallel RAM over a tristate bridge to my Cyclone III, running a NIOS2. Using "SignalTap", I've seen the following strange behaviour.

Performing write accesses with the IO-macros:

IOWR: 32 Bit write

IOWR_8DIRECT: 8 Bit write

IOWR_16DIRECT: 16 Bit write

IOWR_32DIRECT: 32 Bit write (as intended)

but performing read accesses:

IORD: 32 Bit read

IORD_8DIRECT: 32 Bit read

IORD_16DIRECT: 32 Bit read

IORD_32DIRECT: 32 Bit read (as NOT intended)

I know, that NIOS2 has 32bit width, but the external memory I use is a DPRAM of an ASIC using 8 bit mode and I somehow need to get a 8-bit read-access working, because the ASIC recognizes each read-access and for example toggles some status flags after it. And thats why it is not sufficient, that NIOS is ignoring the other 24 bits.

I would be glad, if someone has got an answer about the question, if this is a bug or a feature ;) (Or maybe my incompetence).

Thank you,

bye Harry.

5 Replies

  • Altera_Forum's avatar
    Altera_Forum
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    17 years ago

    well this is a combination of a bug and a feature :-)

    and this has been discussed since discovered but the only workaround i found so far is to monitor the byteenables they tell you what byte of the 32 bit is realy needed and if there is an access to such an unwanted byte to surpress the execution.

    yes this i a very big disapointing thing with external devices that do something if they recognize a read access.

    This is very hard to find for softwareguys if a status bit is changed and you think you haven't read from that address

    to be honest, i haven't look at it with signaltap and quartus 9.1 if this bug/feature is still present.
  • Altera_Forum's avatar
    Altera_Forum
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    17 years ago

    Hi MSchmitt,

    thanks for your answer.

    Well, I will think about implementing your hint, even though it is not the way as "IORD_8DIRECT" is expected to work. This is really disappointing!

    I've tried it with quartus 9.0sp2 and NIOSII 9.0 IDE, with SignalTap AND with an external digital logic analyzer, so this is not SignalTap related but really happens in practice.

    Is there a bugreport-list to report this one?
  • Altera_Forum's avatar
    Altera_Forum
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    17 years ago

    well after i discovered this behavioral in 2005, there were several discussion with FAE's and Altera and MySupport telling them that with this buggy feature it is nearly impossible to attach any existing profibus chip (thats an industrial network protocoll) to the tristate bridge as these devices react upon read access to some locations. some status bits a cleared and you try to dig down why as you don't understand that behavioral from software side.....

    but if you and other complain about that then there might be a chance that this gets fixed but i fear this behavioral will exists for ever and ever and remain for compatibilty purposes in the future :-)

    yes it is not signaltal related, i use signaltap to quick check such things without wireing some probes.
  • Altera_Forum's avatar
    Altera_Forum
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    17 years ago

    Here is what I would do to work around your problem:

    Did you create a custom SoPC builder component or connect the component directly to an avalon tri-state bridge?

    Regardless, you need to configure your component as a 32-bit wide component. Let SoPC builder think that your external component is 32-bits wide. Then you can access it with any of the macros. You of course will only connect the lower 8-bits and disregard the upper 24. And of course you will do nothing with the upper 24-bits of data when you perform a read.

    This guarantees only one access to the peripheral each time the NIOS performs a read.

    Jake
  • Altera_Forum's avatar
    Altera_Forum
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    17 years ago

    jake, that is only a workaround and makes it nearly impossible to put something link a structure over such a memory where you have registers and memory areas within one external device, thats what ALL (yes all) profibus chips do that came across my desk over the last 13 years. these devices have serveral memory areas and lots of registers but only 1 chipselect. for some reasons like transfer speed you want to use memcopy and use a bit complex structures to make these devices handsome.

    so what i did was to implement an sopc custom ip that is a tri state slave but monitors the byteenables during read access and disscards the not needed byte reads and delivers 0x00 instead, same value as the avalon switch fabric would deliver.

    your suggestion could be of course a solution in some cases.

    but i still wish that altera would handle these not needed reads and remove them.