Interval timer problem

Hello.

// global variablesint err; 
// handler
static void handle_timer(void* context)
{
    IOWR_ALTERA_AVALON_TIMER_CONTROL(timer_base, ALTERA_AVALON_TIMER_CONTROL_STOP_MSK); //disable interrupt
    IOWR_ALTERA_AVALON_TIMER_STATUS(timer_base, 0); //clear flag
    IOWR_ALTERA_AVALON_PIO_DATA(PIO_BASE, 1);
    timer_exit();
    err = 1;
    return;
}
// set handler
void timer_init(alt_u32 _base, alt_u32 _interrupt, alt_u32 _irq)
{
    timer_base = _base; 
    timer_interrupt = _interrupt;
    timer_irq = _irq;
    alt_ic_irq_disable (timer_interrupt, timer_irq);//disable interrupt
    alt_ic_isr_register(timer_interrupt, timer_irq, handle_timer, NULL, NULL); break;
    return;
}
// reset / set timeout 
void timer_set_period(alt_u32 timer_period)
{
    timer_period = HIGHT_RES_TIMER_LOAD_VALUE * timer_period;
    IOWR_ALTERA_AVALON_TIMER_PERIODL(timer_base, timer_period&ALTERA_AVALON_TIMER_PERIODL_MSK);            //write timer period l
    IOWR_ALTERA_AVALON_TIMER_PERIODH(timer_base, (timer_period>>16)&ALTERA_AVALON_TIMER_PERIODH_MSK);    //write timer period h
    return;
}
// start counting
void timer_start(void)
{
    IOWR_ALTERA_AVALON_TIMER_CONTROL(timer_base, ALTERA_AVALON_TIMER_CONTROL_STOP_MSK); //stop timer, disable interrupt
    IOWR_ALTERA_AVALON_TIMER_STATUS(timer_base, 0);                                     //clear flag
    IOWR_ALTERA_AVALON_TIMER_CONTROL(timer_base, (    ALTERA_AVALON_TIMER_CONTROL_ITO_MSK |
                                                    ALTERA_AVALON_TIMER_CONTROL_START_MSK)); //start timer, enable interrupt
    return;
}
// pause counting
void timer_stop(void)
{
    IOWR_ALTERA_AVALON_TIMER_CONTROL(timer_base, ALTERA_AVALON_TIMER_CONTROL_STOP_MSK); //stop timer, disable interrupt
    IOWR_ALTERA_AVALON_TIMER_STATUS(timer_base, 0);                                     //clear flag
    return;
}
// timer deactivation 
void timer_exit(void)
{
    IOWR_ALTERA_AVALON_TIMER_CONTROL(timer_base, ALTERA_AVALON_TIMER_CONTROL_STOP_MSK); //stop timer, disable interrupt
    IOWR_ALTERA_AVALON_TIMER_STATUS(timer_base, 0);                                     //clear flag
    alt_ic_irq_disable (timer_interrupt, timer_irq);//disable interrupt
    return;
}
// timer usage
int foo(void)
    {
        int nop; 
        err = 0;
        
/*A*/    IOWR_ALTERA_AVALON_PIO_DATA(PIO_BASE, 0);    //set PIO
/*B*/    timer_init(HIGHT_RES_TIMER_BASE, HIGHT_RES_TIMER_IRQ_INTERRUPT_CONTROLLER_ID, HIGHT_RES_TIMER_IRQ);
/*C*/    timer_set_period(10);
/*D*/    timer_start();
        while(err == 0)
        {nop=0;}        //waiting for timer
        timer_exit();
        return 1;
    }

/*
 * hight_res_timer configuration
 *
 */# define ALT_MODULE_CLASS_hight_res_timer altera_avalon_timer# define HIGHT_RES_TIMER_ALWAYS_RUN 0# define HIGHT_RES_TIMER_BASE 0x1003520# define HIGHT_RES_TIMER_COUNTER_SIZE 32# define HIGHT_RES_TIMER_FIXED_PERIOD 0# define HIGHT_RES_TIMER_FREQ 75000000u# define HIGHT_RES_TIMER_IRQ 1# define HIGHT_RES_TIMER_IRQ_INTERRUPT_CONTROLLER_ID 0# define HIGHT_RES_TIMER_LOAD_VALUE 74ull# define HIGHT_RES_TIMER_MULT 1.0E-6# define HIGHT_RES_TIMER_NAME "/dev/hight_res_timer"# define HIGHT_RES_TIMER_PERIOD 1.0# define HIGHT_RES_TIMER_PERIOD_UNITS "us"# define HIGHT_RES_TIMER_RESET_OUTPUT 0# define HIGHT_RES_TIMER_SNAPSHOT 1# define HIGHT_RES_TIMER_SPAN 32# define HIGHT_RES_TIMER_TICKS_PER_SEC 1000000u# define HIGHT_RES_TIMER_TIMEOUT_PULSE_OUTPUT 0