Interfacing custom module with Nios II

According to the pdf file you can set DATA_WIDTH to 128. But the tcl file allows you to select only a 8,16 or 32 bit data width.

I don't know if a 128 width could actually be used and how it would be synthesized. Since Avalon is a 32bit bus, at least 8 bus cycles are required even so.

Then, I'd rather define DATA_WIDTH=32 and span the 128 key data on multiple user_data registers.

Regarding the 1bit signals there's no problem: you can route one single user_data line to your custom logic and discard all the others.