Honored Contributor
Honored ContributorI haven't never used this template but I took a quick look at it and I definitely think this is perfect for you.
Follow these steps: - replace all <slave_template> occurrences with a name you like and place the files into the \altera\<version>\ip\user_components directory - instantiate your Verilog module in slave_template.v, connecting your data i/o (namely the AES key value) to user_datain and user_dataout - add your .v files to the list in the .tcl file - the next time you open sopc builder, the new component will be available; include it in your system - rebuild all - access AES key and results with IOWR and IORD macros, as shown in .h file That's all. I hope I didn't forget anything
