Honored ContributorI am building a Nios2 system that has custom RAM/FLASH. I am trying to use the Interface to User Logic using an 8 bit data bus (inout), 15 address bits, nRD, nWR, and 2 nChipselects. How in tarnation to you set the chip select addresses? The type for the selects are chipselect_n. Need to have exeption and reset addresses pointing to one of the devices.
Please Help ASAP....
Honored ContributorThe chip select address is specified in the main "System Contents" screen of SOPC Builder under the 'Base' column. The reset address for the processor is specified in the 'More "cpu" settings' window.
If you need to decode 2 chip selects, just make your address bus 1 bit wider and use the upper address bit to decode the single chip select out of the nios into 2 separate chip selects for your memory. -- TerryHonored ContributorTerry,
I already figured out how to change the base address, but how do you change the end address. It currently is showing one single byte (0x100000 to 0x100001). You said... "If you need to decode 2 chip selects, just make your address bus 1 bit wider and use the upper address bit to decode the single chip select out of the nios into 2 separate chip selects for your memory." Are you saying to gen 2 chip selects externaly (glue logic) using one SOPC chip select and the upper address bit? RickHonored ContributorThe end address is determined by the base address and the width of the address bus you specified when creating the 'interface to user logic'.
>>Are you saying to gen 2 chip selects externaly (glue logic) using one SOPC chip select and the upper address bit? Yes -- TerryHonored ContributorWoa, Somefingwrong (new Chinees dish)! I think I'm almost there. I have the address width at 16 and the data at 8, but the end address is still wrong. I must be missing something...
RickHonored ContributorMake sure that you have the "Bus Interface Type" set to 'Avalon Memory Slave' in the "Interface to User Logic" setup.
Also, the addresses shown for the address range are byte addresses but since you're using 8-bit wide memory this shouldn't be an issue. -- TerryHonored ContributorStill doesn't work. I already had Avalon Memory Slave selected. Don't Know?????
RickHonored ContributorWell it looks like the SOPC may have a bug. All I did was deltete the whole Interface to user logic and generate a new one. I looks just like the one I couldn't get working, but for some reason this one works.
On a side note: Where in the SDK and IDE/HAL do you set where the stack is? The only memory I have is external using an avalon slave memory bus. I used a single chip select and sub decoded it ouside the SOPC (4 additional chip selects). I may not have any memory connected to the top 3 (expandability). I know that the reset and exception are covered, but how do I setup the stack and data memory? In the IDE, you can select it in the system library preferences, but I never saw where you set the base address (physical). Wouldn't want it to throw it at the higher addresses! RickHonored ContributorRick,
I believe the stack is dynamically allocated out of program memory at runtime. To prevent the unpopulated upper memory from being accessed, I would only generate 2 chip selects in SOPC builder instead of 4. You can reserve 4 pins on your FPGA for RAM chip selects, but you don't need to tell the Nios about them until you're ready to use them. Just tie them to VCC in your top-level FPGA design. In the future, you'll have to regenerate the Nios and connect up the chip selects when you're ready to use them. -- TerryHonored ContributorI meant to say that the stack is dynamically allocated out of data memory at runtime (rather than program memory).
-- Terry
