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Honored Contributor
Honored ContributorInterface to User Logic
I am building a Nios2 system that has custom RAM/FLASH. I am trying to use the Interface to User Logic using an 8 bit data bus (inout), 15 address bits, nRD, nWR, and 2 nChipselects. How in tarnati...
Altera_ForumHonored Contributor
Honored ContributorRick,
I believe the stack is dynamically allocated out of program memory at runtime. To prevent the unpopulated upper memory from being accessed, I would only generate 2 chip selects in SOPC builder instead of 4. You can reserve 4 pins on your FPGA for RAM chip selects, but you don't need to tell the Nios about them until you're ready to use them. Just tie them to VCC in your top-level FPGA design. In the future, you'll have to regenerate the Nios and connect up the chip selects when you're ready to use them. -- Terry
