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Altera_Forum
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15 years ago

impossible to boot ep3c25 from epcs16 - reset_vector problem ?

Hi,

I am developing my first niosII design. It works well when I use a volatile programming file (.sof) but I have issues to program the fpga with an external flash.

I use :

- cycloneIII ep3c25

- flash epcs16 (configuration)

- ssram (nios memory)

- quartus 9.1 sp2

- nios software 10.0

- windows7 x64

The hardware image seems to boot (1 led and 1 screen managed by hw are powered) but NOT the nios.

When i try to run the nios manually (run as niosII hw application in eclipse) I have the following error:

"Verifying 02401800 (99%) / Verify failed between address / 0x2401800 and 0x240181F / Leaving target processor paused"

@02401800 is the epcs_controller base address (=reset_vector @) in the nios.

I don't understand the reason of the failure.

Thanks for helping !

I configure the nios in the sopc builder like that:

- cypress ssram controller

- epcs serial flash controller ("automatically select dedicated AS..." enabled")

- cpu nios : reset_vector = epcs_flash_controller // offset 0x0

exception_vector = ssram // offset 0x20

- other modules: spi_control_port, pio, jtag, sys_clk_timer, sysid...

fpga design/quartus:

- flash pins are set to "use as regular IO"

i use the following method to program the epcs16 :# 1) Convert SOF to Flash

sof2flash --input=file.sof --output=hwimage.flash --epcs --verbose# 2) Convert ELF to Flash

elf2flash --input=../testBoot.elf --output=swimage.flash --epcs --after=hwimage.flash --verbose# 3) Concatenate

cp hwimage.flash hw_sw.flash

cat swimage.flash >> hw_sw.flash# 4) Create HexFile

nios2-elf-objcopy -I srec -O ihex hw_sw.flash hw_sw.hex

Then i create a .jic file with quartus convert pgm file:

- flash_loader : ep3c25

- hex_data : hw_sw.hex (I try absolute and relative addressing)

I also try without concatenation : file.sof and sw.hex (relative addressing) to create the .jic file.

With the same sopc file I have tested the epcs16 flash with the project template "memory test". both write and read operations work.

Thanks for helping again !

SG.

18 Replies

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  • Altera_Forum's avatar
    Altera_Forum
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    15 years ago

    @Waiyung :

    I now use quartus 9.1sp1. I don't use the "compressed bitstream" option.

    I use command line to convert .elf => .hex then i use quartus convert programming file to generate a .jic.

    @Daixiwen :

    I don't know which commands/tools could be used to test the sram externally. I think it is possible by using jtag to control fpga port, but it don't think altera has developed this functionality. It is more complicated than a simple script.

    maybe the simple way to test sram is to develop a "simple" routine in vhdl or C (if onchip memory is big enough) which read and write the whole memory. I will read the memory_test template code to see if I can reduce the size and make it fit in onchip_memory.
  • Altera_Forum's avatar
    Altera_Forum
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    15 years ago

    I try several configurations :

    - reset_vector -> epcs_flash_controller

    - other memory regions in on chip memory (too small for my entire project)

    => it works

    when I replace onchip with sram memory it don't works very well : impossible to boot nios from epcs but hardware image works. I have made several test projects. For some projects it is possible to boot nios with eclipse ide (hw previously loaded with epcs), for others there are some verifying errors when eclipse upload the code...

    I am now trying to reduce "memory test" project to make it fit the onchip memory.
  • Altera_Forum's avatar
    Altera_Forum
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    15 years ago

    Yes Altera developed this functionnality, it is called system console (http://www.altera.com/literature/hb/qts/qts_qii53028.pdf) tools. There are commands to read and write specific addresses, and you should be able to use them to test the memory.

    For the memory test program, you can try and reduce its size by selecting the small drivers option, removing c++ compatibility (I'm not sure this one will reduce the memory footprint though) and changing the compiler optimization option to "optimize for size".
  • Altera_Forum's avatar
    Altera_Forum
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    15 years ago

    I am back again without any clue...

    Thanks for system console tool info Daixiwen, I didn't know this functionality.

    I made my program fit the onchip memory (reset_vector -> epcs) (c++, exit, clean_exit disabled / jtag_small_driver / alt_printf), and it ... works. It reads and writes the whole sram (I used 3 data values : 0x55aa55aa, 0xaa55aa55 and data=x for @ddr=x).

    One interesting thing is that when I use IDE+.sof it works well, but when I use boot from EPCS, nios boot but crash without reaching the end of sram (I know that the program starts and crash during reading/writing sram, but I don't know when). Something is wrong, but what ?

    The same program (compiled with all functionalities) in sram which rd/wr onchip works well both with IDE and EPCS methods. Does it works because the program is smaller than my project ? Quartus & bsp editor setting are very similar so I don't understand why my project doesn't work.

    I have also checked schematics, connections quality on the board. The more I try different things, the less I see the solution. Maybe I should have asked it for christmas ^^
  • Altera_Forum's avatar
    Altera_Forum
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    15 years ago

    Perhaps the stack and/or heap are in sram!

    Check the values of the registers/addresses.
  • Altera_Forum's avatar
    Altera_Forum
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    15 years ago

    Sorry for replying late, but I was really bored with the absence of any progress in my issue, so I left it for a few days.

    I made several modifications and now it works. The entire design (nios+hw) boot from flash. I hope it is not temporary.

    These modifications are :

    - The connection with sram electronic schematic was taken from the niosII (cycII) eval kit which has the same configuration (epcs, cypress sram). there are some inversion in some address and byte enable pins, so I corrected it in the fpga pin out.

    - My prototype board seems to have random problems, maybe due to bad contacts (bad soldering ?), so I made another one.

    - In the bsp editor, I disabled some options (which seem to be enabled randomly in new projects ?) : allow_code_at_reset, enable_alt_load... (see http://www.altera.com/literature/hb/nios2/edh_ed5v1_02.pdf page 2-55).

    After testing and reading a lot of things, I wonder why altera change so often its softwares versions. Stability and reliability before anything else !!!

    Thanks again for answers.

    Seb