Forum Discussion
Altera_Forum
Honored Contributor
15 years agoSorry for replying late, but I was really bored with the absence of any progress in my issue, so I left it for a few days.
I made several modifications and now it works. The entire design (nios+hw) boot from flash. I hope it is not temporary. These modifications are : - The connection with sram electronic schematic was taken from the niosII (cycII) eval kit which has the same configuration (epcs, cypress sram). there are some inversion in some address and byte enable pins, so I corrected it in the fpga pin out. - My prototype board seems to have random problems, maybe due to bad contacts (bad soldering ?), so I made another one. - In the bsp editor, I disabled some options (which seem to be enabled randomly in new projects ?) : allow_code_at_reset, enable_alt_load... (see http://www.altera.com/literature/hb/nios2/edh_ed5v1_02.pdf page 2-55). After testing and reading a lot of things, I wonder why altera change so often its softwares versions. Stability and reliability before anything else !!! Thanks again for answers. Seb