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Altera_Forum's avatar
Altera_Forum
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20 years ago

IDT 71V416 SRAM Timing

Hi

I've built a custom board, using 4 IDT71V416 SRAMS to provide 512K x 32 bits. I have used the Altera supplied components, and clock at 40 MHz.

Like others, I have seen my program run wild. Apparently, there is some incentive to add a setup state to the memory.

Can anyone tell me....

1. Does the added setup state help with the IDT 71V416?

2. Can I patch the .PTF file for my own design? Or should I create a new custom user logic that's just like the supplied 71V416 but with a setup state?

3. If patching is OK, do I just change the line "Setup Time = 0" to be "Setup Time = 1" ?

4. The problem "feels" like a stack overflow. Is there some place I can specify stack sizes? Or is it entire available memory less whatever is used?

Thanks guys and gals

1 Reply

  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    20 years ago

    For the benefit of all, I have at least partially addressed the problem. The following may help others...

    Yes, as others have said here, memory speed does seem to be at least part of the problem. The issue surfaced when I moved my memory from onchip to external.

    The easy way to slow down the program is to edit the .pl file. Your structure may differ, but mine was at

    C:\altera\kits\nios2\components\altera_nios_dev_kit_stratix_edition_sram2

    Editing the class.ptf file doesn't work. Apparently SOPC looks at the mk_sram.pl file and adds wait states depending on the clock speed chosen for the design. In my case, at 40 MHz, it didn't add any.

    By editing the mk_sram.pl file to add wait states above 39 MHz, I caused this to happen.

    I still have issues to resolve, but this was a big step in the right direction.