IDT 71V416 SRAM Timing

For the benefit of all, I have at least partially addressed the problem. The following may help others...

Yes, as others have said here, memory speed does seem to be at least part of the problem. The issue surfaced when I moved my memory from onchip to external.

The easy way to slow down the program is to edit the .pl file. Your structure may differ, but mine was at

C:\altera\kits\nios2\components\altera_nios_dev_kit_stratix_edition_sram2

Editing the class.ptf file doesn't work. Apparently SOPC looks at the mk_sram.pl file and adds wait states depending on the clock speed chosen for the design. In my case, at 40 MHz, it didn't add any.

By editing the mk_sram.pl file to add wait states above 39 MHz, I caused this to happen.

I still have issues to resolve, but this was a big step in the right direction.