Occasional ContributorHi,
I want to have a soft core NIOS 2 /e, and to the Avalon bus of this processor I want to attach a I2C master. This I2C master should export 2 lines (SDA, SCK) and this two lines (and pull ups) were connected to temp sensors.
But doing so, I get a running design, compiling without error, but the isc interface looking strange. What di I miss?
Thanks for helping.
With best regards
Gerhard
ModeratorHi @Gerhard56,
Thank you for posting in Intel community forum, hope this message find you well and apologies for the delayed in response.
Can you please explain more on the what is looking strange on the design for us to better understand the situation.
In the meantime, I would recommend to check on the following reference design on I2C master with NIOS example here which contain a simple C code to test on the I2C interface.
Warm regards.
BB
Occasional ContributorHi BoonBang,
I expected two lines, sda and scl, but I get 4 lines ...
Later on I found out, that I have to add some additional buffers to implement the correct hardeware behaviour, cause the FPGA cant do that simpler.
Maybe it will be a nice idea, to include grafics and code in the description so it is easier to start with.
Thanks for the sample. I need a I2C master interface, hope I can find something, but to have a I2C slave ist very good too.
With best regards
Gerhard
Occasional Contributor... oh, see the your text now. You wanted to send me the i2c_master_sampe_1.zip but I get i2C_slave_sample_1.zip.
With best regads
Gerhard
