I am testing my project on Atum Nios V starter kit from terasic, which bases on Agilex 3 (A3CZ135BB18AE7S) and SDRAM(IS42VM32160G-6BLI). my purpose is, realize a Nios V system with RTOS and use the SDRAM as the program ram of the RTOS.My question: Agilex 3 is supported only by the higher version such as quartus pro 25.3, and the SDRAM ip is supported by previous old version quartus. do you have any solution that i can reuse the avalon interface SDRAM IP core on Agilex 3?thanks.

Hi Rainwang,I can confirm that the IP used for the DE23-lite board does work on the Atum A3. I just took the verilog files and used them to create a module in Platform designer. I was then able to read and write to the SDRAM from a RiscFree c program.Regards

got it. thank you for the support, i am using the example for further evaluation.

Hello,Terasic has released, A Nios V processor-based design example demonstrating how to sequentially display bitmap image files from a Micro SD card on an HDMI monitor on github. This design includes SDRAM controller. Here the example design path is (github.com/terasic/Atum-A3-Nano/tree/rel/25.1/picture_viewer_1080p) This example design is targeted for Terasic Atum Nios V starter kit. Please refer this design and modify as per your design requirement utilizing Nios V and SDRAM controller.Please let me know if you have any further questions. Thanks

Terasic told me that the DE23-Lite board uses the same FPGA - SDRAM combination and there is an example there. I used it as a starting point for my Atum A3 board.Now if only they would show us how to use the ethernet port!

Hello, Ethernet example design for DE23-lite board is not yet released to public. Tentative plan is to get this example design by then end of Q4'2025. I will let you know once the example design is available. Till then stay tuned!.Thanks

How to use SDRAM IP core on Agilex 3? | Altera Community

14 Replies

AvinashTh_Altera
New Contributor
3 months ago
Hello,
Terasic has released, A Nios V processor-based design example demonstrating how to sequentially display bitmap image files from a Micro SD card on an HDMI monitor on github. This design includes SDRAM controller. Here the example design path is (github.com/terasic/Atum-A3-Nano/tree/rel/25.1/picture_viewer_1080p) This example design is targeted for Terasic Atum Nios V starter kit.
Please refer this design and modify as per your design requirement utilizing Nios V and SDRAM controller.
Please let me know if you have any further questions.
Thanks
- Rainwang
  Contributor
  2 months ago
  got it. thank you for the support, i am using the example for further evaluation.
  - BoonBengT_Altera
    Moderator
    1 month ago
    Dear Customer,
    
    As clarification is being provided. Hence if there are no further inquiries during this period, Will allow the community to assist with any future follow-up questions.
    
    Thank you for engaging with us!
    
    Best regards,
    Altera Technical Support

Forum Discussion

How to use SDRAM IP core on Agilex 3?

14 Replies

Recent Discussions

University Program IP for NiosV

Nios II IDE File Name too long error

Unable to load Ashling Riscfree NiosV libraries

Correct way to use mSGDMA with a NIOSV/m processor on a MAX10 FPGA

AshlingRISCFree IDE Build system: 'source directory does not appear to contain CMakeLists.txt"