How to implement an NoC (Network on Chip) in my DE1-SOC (Nios-II, Qsys)?

100 cores of what?

Nios relies on the Avalon Bus - usually with the Nios acting as the master and other units connected via a memory mapped avalon interface.

This way you can have any existing IP or any other IP you chose to design yourself (as avalon is a straight forward interface, very similar to AXI).

NoC is usually a term used for Asic, not FPGA.

--- Quote Start ---

100 cores of what?

Nios relies on the Avalon Bus - usually with the Nios acting as the master and other units connected via a memory mapped avalon interface.

This way you can have any existing IP or any other IP you chose to design yourself (as avalon is a straight forward interface, very similar to AXI).

NoC is usually a term used for Asic, not FPGA.

--- Quote End ---

So, basicaly Altera is lying to the publich with the "NoC" based interconnection. https://www.altera.com/en_us/pdfs/literature/wp/wp-01149-noc-qsys.pdf

While that article is accurate, and Qsys does do those things, fitting 100 cores of NIOS on a DE1-SOC isn't realistic.

If not simply because of the NIOS core resource utilization, then because of the associated adapter and interconnect logic that Qsys generates (see Table 2 on page 11 of that article).

So if your answer to Daixiwen's question of "100 cores of what?" is "NIOS of course!!!", then the answer is no. Either don't use NIOS or don't use 100 instances.

--- Quote Start ---

While that article is accurate, and Qsys does do those things, fitting 100 cores of NIOS on a DE1-SOC isn't realistic.

If not simply because of the NIOS core resource utilization, then because of the associated adapter and interconnect logic that Qsys generates (see Table 2 on page 11 of that article).

So if your answer to Daixiwen's question of "100 cores of what?" is "NIOS of course!!!", then the answer is no. Either don't use NIOS or don't use 100 instances.

--- Quote End ---

Going back to the NoC topic, is there any chance to make utilization of this NoC in the FPGA? I mean, the basic idea of NoC, has a number of cores (20 - 100) communicated with a network subsystem of routers, this bring you the posibility of choose a topology among the cores, or if one of the cores fail, routers routes data trough other paths (it's fault tolerant). I expected to find something like this in the so-called NoC of Qsys, but it seems it's something totally different.

The article you have found and skimmed isn't an IP datasheet or user manual for a "NoC Creators Toolbox". It's a white paper describing how Altera has used NoC approach to benefit their customers: lower resource utilization, increased Fmax compared to SOPC Builder (the predecessor) and why everybody would be so much better off if they migrated to Qsys.

--- Quote Start ---

is there any chance to make utilization of this NoC in the FPGA?

--- Quote End ---

On one hand, a NoC is created every time you click "Generate" in Qsys. But on the other hand, you don't have any direct control of it and there is no access to the lower level primitives that Qsys uses to construct your own hand crafted.

There isn't anything preventing you from creating a torus in Qsys, and you could argue that Qsys is better than some alternatives for doing so. e.g. create a "node" Qsys subsystem with processor+memory, then write a TCL script to instantiate your torus and make the interconnects.

If you take this approach, then when your torus has (n) nodes you will have at least (n+1) "networks" - one inside each subsystem instance, and one at your toplevel.

--- Quote Start ---

If you described the problem rather than repeat this stuff about the NoC, then maybe we could help you design an appropriate system.

--- Quote End ---

You also need to decide what you mean by a NoC. Newer FPGAs provide a fabric that is physically designed for such architectures with higher-level pathways available to a larger degree. Implementing a NoC in a raw FPGA could really strain your timing resources depending on architecture, as you are overlaying a significant number of communication lines on top of the core fabric. Qsys generates a perfectly acceptable routing network, otherwise you can license IP for something like the Arteris NoC used in the Arria 10, or you can even license the ARM AMBA interconnect components.

But a NoC is just a communications interconnect-- I'm in agreement. Figure out exactly what you need or are trying to do. Remember that an FPGA is hardware/firmware, NOT software, so imagine how such a system would be implemented in hardware before anything else.

--- Quote Start ---

Going back to the NoC topic, is there any chance to make utilization of this NoC in the FPGA? I mean, the basic idea of NoC, has a number of cores (20 - 100) communicated with a network subsystem of routers, this bring you the posibility of choose a topology among the cores, or if one of the cores fail, routers routes data trough other paths (it's fault tolerant). I expected to find something like this in the so-called NoC of Qsys, but it seems it's something totally different.

--- Quote End ---

Also, this is asking a huge amount of a designed architecture. Adding fault-tolerance is not the purpose of a communications architecture; that would require some sort of supervisory layer on top of the architecture. You'd also need to design a specialized interconnect that could bypass a node based on certain conditions. It really all comes sown to needs! Even AXI breaks down pretty spectacularly if you don't use a timeout block.