Honored Contributor
Honored ContributorThe article you have found and skimmed isn't an IP datasheet or user manual for a "NoC Creators Toolbox". It's a white paper describing how Altera has used NoC approach to benefit their customers: lower resource utilization, increased Fmax compared to SOPC Builder (the predecessor) and why everybody would be so much better off if they migrated to Qsys.
--- Quote Start --- is there any chance to make utilization of this NoC in the FPGA? --- Quote End --- On one hand, a NoC is created every time you click "Generate" in Qsys. But on the other hand, you don't have any direct control of it and there is no access to the lower level primitives that Qsys uses to construct your own hand crafted. There isn't anything preventing you from creating a torus in Qsys, and you could argue that Qsys is better than some alternatives for doing so. e.g. create a "node" Qsys subsystem with processor+memory, then write a TCL script to instantiate your torus and make the interconnects. If you take this approach, then when your torus has (n) nodes you will have at least (n+1) "networks" - one inside each subsystem instance, and one at your toplevel.
