How to get 32bit system with DDR sdram

in this case the avalon master used two read or write cycles to access

32 bit in the 16 bit memory.

see quartus II version 5.1 handbook volume 4

"Native Address Alignment & Dynamic Bus Sizing"

--- Quote Start ---

originally posted by fischer@Aug 14 2006, 02:05 PM

in this case the avalon master used two read or write cycles to access

32 bit in the 16 bit memory.

see quartus ii version 5.1 handbook volume 4

"native address alignment & dynamic bus sizing"

<div align='right'><{post_snapback}> (index.php?act=findpost&pid=17592)

--- quote end ---

--- Quote End ---

No, it doesn&#39;t work this way for the EP2C35 (Cyclone II Nios II) board. For the DDR controller, the local (Avalon) side is 32 bits and the interface side is 16 bits. Since this is a DDR (dual data rate) controller [2*16=32], it&#39;s capable of combining two 16 bit interface reads into one 32 bit "local side" read.

Cheers,

- slacker

Then,If I get the 32bits system in my new board, Must I use two mt46v16m16tg chip???this chip is 16bits data bus.

thanks.