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Altera_Forum
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20 years ago

How to allocation ISR into a faster memory device

Hi everybody:

In order to speed up interrupt responding time, I hope to allocate exception handler and all ISR into a tightly-coupled memory(TCM). So, I do the following steps:

1. add a onchip memory(dual ports) into system and connect it to CPU's tightly-coupled data master and instruction master

2. point exception address to this onchip memory(this step will allocate exception handler into onchip memory)

3. In NiosII IDE, in order to allocate ISR code in onchip memory, I check the option 'Use a separate exception stack'.

but after compiling projecct, I found that all ISRs code are not allocated in onchip memory but in SDRAM.

WHY?

Then I tried the other way, Advanced Placement Options:

one piece of my code is as the following shows:

void INTERRUPT_1_ISR __attribute__ ((section (".onchip_memory_s1.text"))) (void* context, alt_u32 id)

but the following compiling error occur:

error: storage size of `INTERRUPT_1_ISR' isn't known interruptible_and_TCM.c

Is my code's format wrong?

I wrote it base on the Advanced Placement Options which is described in page70 of document "NiosII Software developer's handbook".

Thanks any help very much.

regards. http://forum.niosforum.com/work2/style_emoticons/<#EMO_DIR#>/tongue.gif

2 Replies

  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    20 years ago

    Hi,

    Now, I have solved the second problem.

    The fact is that I&#39;m in wrong format.

    But I still have some uncomfirming issues:

    (1)The effect of the option of system library property: "Use a seperate exception stack"

    I using a dual port tightly-coupled memory(OCM_s1, OCM_s2; note OCM_s1 connecting to instruction master and OCM_s2 connecting to data master) which were connected to cpu&#39;s tightly-coupled data master and instruction master and set the exception address to OCM_s1.

    Because OCM_s1 connecting to instruction master, in source code, in order to allocate ISR code into onchip memory, I made the following attribute:

    void INTERRUPT_1_ISR(void* context, alt_u32 id) __attribute__ ((section (".OCM_s1")));

    But the following error occurred:

    /cygdrive/c/altera/nios2/bin/nios2-gnutools/H-i686-pc-cygwin/bin/../lib/gcc/nios2-elf/3.4.1/../../../../nios2-elf/bin/ld: section .onchip_memory_s1 [00800020 -> 008000a3] overlaps section .exceptions [00800020 -> 008001d3]

    Then, I modified the memory to OCM_s2

    void INTERRUPT_1_ISR(void* context, alt_u32 id) __attribute__ ((section (".OCM_s2")));

    And everything work fine.

    So, I&#39;m confused.

    OCM_s2 connecting to data master but ISR is instruction code, how can nios execute instruction through data master???

    Thanks any help! http://forum.niosforum.com/work2/style_emoticons/<#EMO_DIR#>/happy.gif

    best wishes.
  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    20 years ago

    --- Quote Start ---

    originally posted by david_cai@Dec 12 2005, 02:18 AM

    but i still have some uncomfirming issues:

    (1)the effect of the option of system library property: "use a seperate exception stack"

    --- Quote End ---

    The separate exception stack is not for ISR code, just for the stack that is used by the ISR code. You must add a tightly coupled data memory that is only connected to the cpu&#39;s tightly coupled data master and specify this as the separate exception stack.

    For the ISR code use the dual port tcm that you have. This is only connected to the cpu&#39;s tightly coupled instruction master and the cpu&#39;s data master (not the tightly coupled data master).

    Use __attribute__ ((section(".exceptions"))) when declaring a function that should be placed into this memory. If you call an inline function from such an ISR it will be placed into the same section (no __attribute__ required).