How to allocation ISR into a faster memory device

Hi,

Now, I have solved the second problem.

The fact is that I'm in wrong format.

But I still have some uncomfirming issues:

(1)The effect of the option of system library property: "Use a seperate exception stack"

I using a dual port tightly-coupled memory(OCM_s1, OCM_s2; note OCM_s1 connecting to instruction master and OCM_s2 connecting to data master) which were connected to cpu's tightly-coupled data master and instruction master and set the exception address to OCM_s1.

Because OCM_s1 connecting to instruction master, in source code, in order to allocate ISR code into onchip memory, I made the following attribute:

void INTERRUPT_1_ISR(void* context, alt_u32 id) __attribute__ ((section (".OCM_s1")));

But the following error occurred:

/cygdrive/c/altera/nios2/bin/nios2-gnutools/H-i686-pc-cygwin/bin/../lib/gcc/nios2-elf/3.4.1/../../../../nios2-elf/bin/ld: section .onchip_memory_s1 [00800020 -> 008000a3] overlaps section .exceptions [00800020 -> 008001d3]

Then, I modified the memory to OCM_s2

void INTERRUPT_1_ISR(void* context, alt_u32 id) __attribute__ ((section (".OCM_s2")));

And everything work fine.

So, I'm confused.

OCM_s2 connecting to data master but ISR is instruction code, how can nios execute instruction through data master???

Thanks any help! http://forum.niosforum.com/work2/style_emoticons/<#EMO_DIR#>/happy.gif

best wishes.