How do I get SSRAM to run at 125MHz?

For the CycloneII kit, I had the same problem.

I adjusted the skew to -1.5ns, then the SSRAM worked on 120Mc.

So indeed it is a matter of adjusting the skew to the correct value. Trial and error, or following the description in the SSRAM core manual.

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originally posted by svhb@Sep 1 2006, 06:13 AM

for the cycloneii kit, i had the same problem.

i adjusted the skew to -1.5ns, then the ssram worked on 120mc.

so indeed it is a matter of adjusting the skew to the correct value. trial and error, or following the description in the ssram core manual.

<div align='right'><{post_snapback}> (index.php?act=findpost&pid=18007)

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I tried -4.8ns and it verified the code after downloading it from the IDE, but nothing happened after that. I&#39;m doing a compile with -1.5ns now.

Has anyone successfully used SSRAM at 125 (or higher) MHz on a Stratix II development kit? If so what skew did you use for the SSRAM clock?

Alternatively, what signals should I be looking at on a logic analyzer to determine what the ideal skew for my design is? SSRAM uses quite a few more signals than the mictor connector provides.

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originally posted by bkucera+sep 6 2006, 04:13 pm--><div class='quotetop'>quote (bkucera @ sep 6 2006, 04:13 pm)</div>

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<!--quotebegin-svhb@Sep 1 2006, 06:13 AM

for the cycloneii kit, i had the same problem.

i adjusted the skew to -1.5ns, then the ssram worked on 120mc.

so indeed it is a matter of adjusting the skew to the correct value. trial and error, or following the description in the ssram core manual.

<div align='right'><{post_snapback}> (index.php?act=findpost&pid=18007)

--- quote end ---

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I tried -4.8ns and it verified the code after downloading it from the IDE, but nothing happened after that. I&#39;m doing a compile with -1.5ns now.

Has anyone successfully used SSRAM at 125 (or higher) MHz on a Stratix II development kit? If so what skew did you use for the SSRAM clock?

Alternatively, what signals should I be looking at on a logic analyzer to determine what the ideal skew for my design is? SSRAM uses quite a few more signals than the mictor connector provides.

<div align='right'><{post_snapback}> (index.php?act=findpost&pid=18119)</div>

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On the Startix II board I ran the SSRAM at a couple of speeds sucessfully however I didn&#39;t do any math described inth the SSRAM document (so take these numbers with a grain of salt):

(2 cycles of read latency)

120MHz -4.8ns

125Mhz -3.5ns

My suggestion if you don&#39;t want to do the timing math from the report file:

1) Minimize your design so it compiles fast containing Nios II (f), JTAG UART, Timer, SysID, Tri-state Bridge, and SSRAM component (and generate)

2) Turn on smart compile in your Quartus II project settings

3) Pick some frequency you want to run your SSRAM (and keep this constant between steps 4-6)

4) Pick a reasonable amount of phase shift (look at the Cyclone II numbers to start you off in the right direction, note these are not directly applicable to Stratix II)

5) Compile and try it out

6) From there just slide the clock by adjusting the phase shift and find the range that works.

Also just in case there is any confusion, when you use a skewed clock to drive the SSRAM component you still need to use a seperate clock that you set for the SSRAM in SOPC Builder. The reason for using the skewed clock is to realign the data so that it can be captured sucessfully on the Avalon clock domain. So using my 125MHz -3.5ns example above I would have sent a clock into SOPC Builder at 125MHz but with no skew.