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Altera_Forum's avatar
Altera_Forum
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14 years ago

Help:DE4 can't run simple socket server normally

I make a qsys hardware for DE4 board,and intend to run a simple socket server

but always failed.

attach my qsys file and information for run simple socket server.

# ########run information in nios ii 11.1

InterNiche Portable TCP/IP, v3.1

Copyright 1996-2008 by InterNiche Technologies. All rights reserved.

prep_tse_mac 0

Your Ethernet MAC address is 00:07:ed:ff:ed:15

prepped 1 interface, initializing...

[tse_mac_init]

INFO : TSE MAC 0 found at address 0x05000000

INFO : PHY Marvell 88E1111 found at PHY address 0x00 of MAC Group[0]

INFO : PHY[0.0] - Automatically mapped to tse_mac_device[0]

INFO : PHY[0.0] - Restart Auto-Negotiation, checking PHY link...

INFO : PHY[0.0] - Auto-Negotiation PASSED

INFO : PCS[0.0] - Configuring PCS operating mode

INFO : PCS[0.0] - PCS SGMII mode enabled

INFO : PHY[0.0] - Checking link...

INFO : PHY[0.0] - Link established

INFO : PHY[0.0] - Speed = 100, Duplex = Full

OK, x=0, CMD_CONFIG=0x00000000

MAC post-initialization: CMD_CONFIG=0x04000203

[tse_sgdma_read_init] RX descriptor chain desc (1 depth) created

mctest init called

IP address of et1 : 0.0.0.0

Created "Inet main" task (Prio: 2)

Created "clock tick" task (Prio: 3)

DHCP timed out, going back to default IP address(es)

Simple Socket Server starting up

[sss_task] Simple Socket Server listening on port 30

Created "simple socket server" task (Prio: 4)

11 Replies

  • Altera_Forum's avatar
    Altera_Forum
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    14 years ago

    Did you define a valid default ip address?

    The line IP address of et1 : 0.0.0.0

    seems indicate no ip address has been defined.
  • Altera_Forum's avatar
    Altera_Forum
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    14 years ago

    First thanks for you attation to my question.

    I use DHCP Client to get ip. //but I can't work.

    or if I set the ip address,the simple socket server run,but I can't ping the DE4

    I am confused!

    --- Quote Start ---

    Did you define a valid default ip address?

    The line IP address of et1 : 0.0.0.0

    seems indicate no ip address has been defined.

    --- Quote End ---

  • Altera_Forum's avatar
    Altera_Forum
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    14 years ago

    If you want to use DHCP you need a DHCP server on your network. Do you have it?

    During initial testing you'd better disable DHCP and use a fixed well known IP address.

    If you can't ping it, there are a number of possible reasons:

    - your pc is not configured with the same subnet as the DE4 board. Check network settings on your pc

    - your fpga design is not fully constrained and it possibly has timing problems

    - other flaws in fpga design (i.e. pin assignment): did you use a standard sample design or did you build it from scratch?

    - you missed something in Nios bsp or application settings
  • Altera_Forum's avatar
    Altera_Forum
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    14 years ago

    thanks again!

    I had a dhcp server, and I can run well with the DE4 sample(sopc builder). I just make a project with qsys reference to the DE4 sample and altera ethernet sample.

    I want run cpu with high Fmax, 150Mhz. but I can't work first!

    so, I think I connect the network correctly and the dhcp server is ok.

    maybe somewhere is wrong,I will only debug and modify it with my effort.

    --- Quote Start ---

    If you want to use DHCP you need a DHCP server on your network. Do you have it?

    During initial testing you'd better disable DHCP and use a fixed well known IP address.

    If you can't ping it, there are a number of possible reasons:

    - your pc is not configured with the same subnet as the DE4 board. Check network settings on your pc

    - your fpga design is not fully constrained and it possibly has timing problems

    - other flaws in fpga design (i.e. pin assignment): did you use a standard sample design or did you build it from scratch?

    - you missed something in Nios bsp or application settings

    --- Quote End ---

  • Altera_Forum's avatar
    Altera_Forum
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    14 years ago

    What about the initial cpu frequency on the working sample? I guess it was lower than 150MHz you are now using.

    With f>100MHz you must carefully constrain your design in order to meet timing, while for lower frequencies you can afford looser requirements.
  • Altera_Forum's avatar
    Altera_Forum
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    14 years ago

    yes! the working sample cpu freq is 50MHz.

    and I use 100MHz for nios ii cpu

    meanwhile I get three critical warning .all is about time constraint setup/hold/recovery time. and the Fmax is greater than 100MHz,

    how to constrain the TSE Module time? some advise?

    best wishes

    thanks!
  • Altera_Forum's avatar
    Altera_Forum
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    14 years ago

    A .sdc file comes with TSE. Make sure this file is included in project files, so that TQ uses it.

    Also enable the timing driven synthesis option in project setting

    and possibly follow the other hints from timing optimization advisor (Quartus Tools menu)

    Before any other step, you must get rid of those critical warnings and make sure the design meets timing.
  • Altera_Forum's avatar
    Altera_Forum
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    14 years ago

    thanks all.

    I solve this question.it is not connected well in qsys.

    although I don't solve the critical warnings for timing,the simple socket server can

    work.
  • Altera_Forum's avatar
    Altera_Forum
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    14 years ago

    Although the design is now working, I recommend analysing and solving those critical warnings.

    Keeping them probably doesn't hurt for test purposes, but can lead to very tricky problems if you deploy the design on the field and go into production.

    Problems could occur when you use a different speed grade device, work near the temperature range limits or simply get FPGAs coming with a different production site and this may lead to slightly changes in typical values of your current device.
  • Altera_Forum's avatar
    Altera_Forum
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    14 years ago

    To Cris72:

    thanks for your recommendation,I will focus on the critical warnings and solve it.

    best wishes!