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Altera_Forum's avatar
Altera_Forum
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21 years ago

HALT instruction for NIOSII?

Can the NIOS core be put in a HALT state after initialisation of the system? Basically, I use a DMA controller to transfer data from SDRAM to a small internal dual-port RAM and I want to keep the efficiency of the SDRAM high by using burst mode. I do not need the NIOS during transfer, only the streaming control signals on the avalon bus, so I guess I can just shutdown the core and wake it up again through an interrupt. I could not find a HALT instruction in the NIOS set, is there a solution for this?

Arjan

3 Replies

  • Altera_Forum's avatar
    Altera_Forum
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    21 years ago

    > I want to keep the efficiency of the SDRAM high

    If your goal is to keep the instruction master off of the SDRAM while performing

    DMA, you can achieve this with an instruction cache or a small on chip ram:

    Disable interrupts and jump to a polling loop in the on chip ram. How you break the

    loop is up to you, but you could certainly poll the DMA status register.

    Regards,

    --Scott
  • Altera_Forum's avatar
    Altera_Forum
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    21 years ago

    Something much simpler that I've done is to change the arbitration settings in the SOPC Builder (under "View" choose "Show Arbitration"). The numbers that are shown for each master/slave connection are the number of consecutive reads or writes that you are guaranteed to get when that master successfully arbitrates for that slave.

    So, in my system, the CPU instruction and data masters' connections to the SDRAM are both set to 1, but my DMA engine's master to SDRAM connection is set to 8. My DMA engine reads 32 32-bit words at a time, so I could have set it to 32, but I decided to compromise it a bit.

    I'm not sure how much complexity (read: logic elements) this adds to the Avalon bus module, but it's worth it; I've seen the bursting in action on SignalTap. Also, it helps a great deal if your DMA master is latency-aware. In my case, this was simple; one state machine handled the address, read, and waitrequest lines, just generating a block of addresses and feeding them through, and another state machine handled the readdata and readdatavalid lines, copying the data into the M4K block.
  • Altera_Forum's avatar
    Altera_Forum
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    21 years ago

    Thanks Scott, Mike. That was very helpful. I decided to go with Mike's solution because that worked right away! I also tried to insert a small instruction cache for the NIOS, but nothing worked anymore after compilation. I didn't try to find the solution, but decided to be lazy for today and choose the easy way.

    Thanks again,

    Arjan