Honored Contributor
Honored ContributorSomething much simpler that I've done is to change the arbitration settings in the SOPC Builder (under "View" choose "Show Arbitration"). The numbers that are shown for each master/slave connection are the number of consecutive reads or writes that you are guaranteed to get when that master successfully arbitrates for that slave.
So, in my system, the CPU instruction and data masters' connections to the SDRAM are both set to 1, but my DMA engine's master to SDRAM connection is set to 8. My DMA engine reads 32 32-bit words at a time, so I could have set it to 32, but I decided to compromise it a bit. I'm not sure how much complexity (read: logic elements) this adds to the Avalon bus module, but it's worth it; I've seen the bursting in action on SignalTap. Also, it helps a great deal if your DMA master is latency-aware. In my case, this was simple; one state machine handled the address, read, and waitrequest lines, just generating a block of addresses and feeding them through, and another state machine handled the readdata and readdatavalid lines, copying the data into the M4K block.
